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56F8335 Datasheet(PDF) 138 Page - Freescale Semiconductor, Inc |
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56F8335 Datasheet(HTML) 138 Page - Freescale Semiconductor, Inc |
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138 / 160 page ![]() 56F8335 Technical Data, Rev. 1 138 Freescale Semiconductor Preliminary Figure 10-10 SPI Master Timing (CPHA = 1) Figure 10-11 SPI Slave Timing (CPHA = 0) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) MSB in Bits 14–1 LSB in tR tC tCL tCL tF tCH tDV(ref) tDV tDI(ref) tR tF Master MSB out Bits 14– 1 Master LSB out SS (Input) tCH SS is held High on master tDS tDH tDI tR tF SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output) MOSI (Input) Slave MSB out Bits 14–1 tC tCL tCL tF tCH tDI MSB in Bits 14–1 LSB in SS (Input) tCH tDH tR tELG tELD tF Slave LSB out tD tA tDS tDV tDI tR |
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