8.3.4 Manual Reset (MR) Input for TLV841M only

The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on

If MR is not controlled externally, then MR can be left disconnected. If the logic signal controlling MR is less than

VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to

Time

(1)

MR

VDD

RESET

(2)

(1) MR pulse width too small to assert RESET

(2) MR voltage not low enough to assert RESET

Figure 8-6. Timing Diagram MR and RESET (TLV841M)

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TLV841

SLVSFO5C – APRIL 2020 – REVISED JULY 2021

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