TLV841 datasheet(19/34 Pages) TI

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8.4 Device Functional Modes

Table 8-1 and Table 8-2 summarizes the various functional modes of the device. Logic high is represented by "H"

and logic low is represented by "L".

Table 8-1. Truth Table for TLV841S

VDD

SENSE

RESET

(ACTIVE-HIGH)

RESET

(ACTIVE-LOW)

VDD < VPOR

—

Undefined

VPOR < VDD < VDD(MIN) (1)

—

VDD ≥ VDD(MIN)

VSENSE< VIT-

VDD ≥ VDD(MIN)

VSENSE > VIT- + VHYS

(1)

When VDD falls below VDD(MIN), undervoltage-lockout (UVLO) takes effect and RESET is held logic low (RESET is held logic high) until

VDD falls below VPOR at which the RESET/RESET output is undefined.

Table 8-2. Truth Table for TLV841M

VDD

RESET

(ACTIVE-HIGH)

RESET

(ACTIVE-LOW)

VDD < VPOR

—

Undefined

VPOR < VDD < VIT-

—

VDD ≥ VIT-

Floating

8.4.1 Normal Operation (VDD > VPOR)

When VDD is greater than VPOR, the reset signal is determined by the voltage on the VDD pin with respect to the

trip point (VIT-)

• MR high: The reset signal corresponds to VDD with respect to the threshold voltage.

• MR low: In this mode, the reset is asserted regardless of the threshold voltage.

8.4.2 Below Power-On-Reset (VDD < VPOR)

When the voltage on VDD is lower than VPOR, the device does not have enough bias voltage to internally pull the

asserted output low or high and reset voltage level is undefined.

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TLV841

SLVSFO5C – APRIL 2020 – REVISED JULY 2021

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