ATA6563 datasheet(6/32 Pages) MICROCHIP

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ATA6562/3

DS20005790E-page 6



2017-2021 Microchip Technology Inc. and its subsidiaries

1.1.2

SILENT MODE (ONLY WITH THE

ATA6562)

A low level on the NSIL pin (available on Pin 5) and on

the STBY pin selects Silent mode. This receive-only

mode can be used to test the connection of the bus

medium. In Silent mode, the ATA6562 can still receive

data from the bus, but the transmitter is disabled and

therefore no data can be sent to the CAN bus. The bus

pins are released to recessive state. All other IC

functions, including the high-speed comparator (HSC),

continue to operate as they do in Normal mode. Silent

mode can be used to prevent a faulty CAN controller

from disrupting all network communications.

1.1.3

STANDBY MODE

A high level on the STBY pin selects Standby mode. In

this mode, the transceiver is not able to transmit or

correctly receive data via the bus lines. The transmitter

and the high-speed comparator (HSC) are switched off

to reduce current consumption.

For ATA6562 only: In the event the NSIL input pin is

set to low in Standby mode, the internal pull-up resistor

causes an additional quiescent current from VIO to

GND. Microchip recommends setting the NSIL pin to

high in Standby mode.

1.1.3.1

Remote Wake-up via the CAN Bus

In Standby mode the bus lines are biased to ground to

reduce current consumption to a minimum. The

ATA6562/3 monitors the bus lines for a valid wake-up

pattern as specified in the ISO 11898-2: 2016. This

filtering helps to avoid spurious wake-up events, which

would be triggered by scenarios such as a dominant

clamped bus or by a dominant phase due to noise,

spikes on the bus, automotive transients or EMI.

The wake-up pattern consists of at least two

consecutive dominant bus levels for a duration of at

least tFilter, each separated by a recessive bus level

with a duration of at least tFilter. Dominant or recessive

bus levels shorter than tFilter are always being ignored.

The complete dominant-recessive-dominant pattern

(as shown in Figure 1-4) must be received within the

bus wake-up time-out time tWake to be recognized as a

valid wake-up pattern. Otherwise, the internal wake-up

logic is reset and then the complete wake-up pattern

must be retransmitted to trigger a wake-up event. Pin

RXD remains at high level until a valid wake-up event

has been detected.

During Normal mode, at a VCC undervoltage condition

or when the complete wake-up pattern is not received

within tWake, no wake-up is signalled at the RXD pin.

When a valid CAN wake-up pattern is detected on the

bus, the RXD pin switches to low to signal a wake-up

request. A transition to Normal mode is not triggered

until the STBY pin is forced back to low by the micro-

controller.

FIGURE 1-4:

TIMING OF THE BUS WAKE-UP PATTERN (WUP) IN STANDBY MODE

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