ATA6563 datasheet(7/32 Pages) MICROCHIP

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DS20005790E-page 7

ATA6562/3

1.2

Fail-safe Features

1.2.1

TXD DOMINANT TIME-OUT

FUNCTION

A TXD dominant time-out timer is started when the

TXD pin is set to low. If the low state on the TXD pin

persists for longer than tto(dom)TXD, the transmitter is

disabled, releasing the bus lines to recessive state.

This function prevents a hardware and/or software

application failure from driving the bus lines to a

permanent dominant state (blocking all network

communications). The TXD dominant time-out timer is

reset when the TXD pin is set to high. If the low state on

the TXD pin was longer than tto(dom)TXD, then the TXD

pin has to be set to high longer 4 µs in order to reset the

TXD dominant time-out timer.

1.2.2

INTERNAL PULL-UP STRUCTURE

AT THE TXD AND STBY INPUT PINS

The TXD and STBY pins have an internal pull-up

resistor to VIO. This ensures a safe, defined state in

case one or both pins are left floating. Pull-up currents

flow in these pins in all states, meaning all pins should

be in high state during Standby mode to minimize the

current consumption.

1.2.3

UNDERVOLTAGE DETECTION ON

PIN VCC

If VVCC or VVIO drops below its undervoltage detection

levels (Vuvd(VCC) and Vuvd(VIO))(see Section 2.0,

Electrical Characteristics), the transceiver switches off

and disengages from the bus until VVCC and VVIO has

recovered. The low-power wake-up comparator is only

switched off during a VCC and VIO undervoltage. The

logic state of the STBY pin is ignored until the VVCC

voltage or VVIO voltage has recovered.

1.2.4

BUS WAKE UP ONLY AT

DEDICATED WAKE-UP PATTERN

Due to the implementation of the wake-up filtering the

ATA6562/3 does not wake-up when the bus is in a long

dominant phase, it only wakes up at a dedicated

wake-up pattern as specified in the ISO 11898-2: 2016.

This means for a valid wake-up at least two

consecutive dominant bus levels for a duration of at

least tFilter, each separated by a recessive bus level

with a duration of at least tFilter must be received via the

bus. Dominant or recessive bus levels shorter than

tFilter are always being ignored. The complete

dominant-recessive-dominant pattern as shown in

Figure 1-4, must be received within the bus wake-up

time-out time tWake to be recognized as a valid wake-up

pattern. This filtering leads to a higher robustness

against EMI and transients and reduces therefore the

risk of an unwanted bus wake- up significantly.

1.2.5

OVERTEMPERATURE

PROTECTION

The

output

drivers

are

protected

against

overtemperature conditions. If the junction temperature

exceeds the shutdown junction temperature, TJsd, the

output drivers are disabled until the junction

temperature drops below TJsd and pin TXD is at high

level again. The TXD condition ensures that output

driver oscillations due to temperature drift are avoided.

See Figure 1-5.

1.2.6

SHORT-CIRCUIT PROTECTION OF

THE BUS PINS

The CANH and CANL bus outputs are short-circuit

protected, either against GND or a positive supply

voltage. A current-limiting circuit protects the

transceiver against damage. If the device is heating up

due to a continuous short on CANH or CANL, the

internal overtemperature protection switches off the

bus transmitter.

1.2.7

RXD RECESSIVE CLAMPING

This fail-safe feature prevents the controller from

sending data on the bus if its RXD line is clamped to

HIGH (e.g., recessive). That is, if the RXD pin cannot

signalize a dominant bus condition because it is e.g,

shorted to VCC, the transmitter within ATA6562/3 is

disabled to avoid possible data collisions on the bus. In

Normal and Silent mode (only ATA6562), the device

permanently compares the state of the high-speed

comparator (HSC) with the state of the RXD pin. If the

HSC indicates a dominant bus state for more than

tRC_det without the RXD pin doing the same, a

recessive clamping situation is detected and the

transceiver is forced into Silent mode. This Fail-safe

mode is released by either entering Standby or

Unpowered mode or if the RXD pin is showing a

dominant (e.g., low) level again. See Figure 1-6.

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