EM62100AGH datasheet(23/60 Pages) EMC

23 / 60 page

EM62100

65 COM/132 SEG STN LCD Driver

Product Specification (V1.1) 09.13.2005

•••• 17

(This specification is subject to change without further notice)

6.8 Display Data Latch Circuit

The display data latch circuit temporarily stores the display data that is output to the

LCD from the display data RAM. The commands such as display normal/reverse

status, display ON/OFF status, and entire display ON/OFF, control only the data within

the latch, but do not change the data within the display data RAM itself.

6.9 Oscillator Circuit

This is an RC type oscillator that generates the display clock. The oscillator circuit is

only enabled when M/S=”H” and CKS=”H”. When CKS=”L” the oscillation stops, and

the display clock is input through the CK terminal.

6.10 Display Timing Generator Circuit

This circuit generates some signals used for displaying the LCD. The display clock, CK

generated by an oscillation clock, generates a clock to the line counter and a latch

signal to the display data latch. The line address of the on-chip RAM is generated in

synchronization with the display clock (CK) and the display data latch circuit in

synchronization, latches the 132-bit display data with the display clock. The display

data, which is read to the LCD driver, is completely independent of the access to the

display data RAM from the microprocessor.

Moreover, the display timing generator circuit generates the common timing and the

liquid crystal alternating current signal (M) from the display clock. It generates a drive

waveform using a 2-frame alternating current drive method, as shown in Figure 6, for

the liquid crystal drive circuit.

VSS

COM0

COM1

RAM

data

SEGn

Figure 6

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