CD1030 datasheet(39/67 Pages) NXP

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Analog Integrated Circuit Device Data

NXP Semiconductors

CD1030

Table 16. Device configuration register

R/W

SPI data bits [23 - 0]

[31-25]

[24]

bit 23

bit 22

bit 21

bit 20

bit 19

bit 18

bit 17

bit 16

0000_001

0/1

FAULT

STATUS

INTflg

Unused

SBPOLL

TIME

VBATP OV

disable

Default on POR

0000

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

WAKE_B

VDDQ Check

INT_B out

Aconfig1

Aconfig0

SP11

SP10

SP9

SP8

1000

1111

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

1111

MISO Return Word

bit 23

bit 22

bits [21 - 0]

0000_001[R/W]

FAULT

STATUS

INTflg

Table 17. Device configuration bits definition

Bit

Functions

Default value

Description

FAULT

STATUS

The FAULT STATUS flag is a read only bit. It is set when a fault occurs and it is cleared upon reading the fault

status register with no fault event is present anymore. It is a global variable and clearing the flag once clears

it for all registers.

INTflg

The INTflg is a read only bit. It is set when an interrupt event occurs and it is cleared upon a read/write

transaction of a register containing the INTflg. It is a global variable and clearing the flag once clears it for all

registers.

21-18

Unused

SBPOLLTIME

Select the polling time for SP channels configured as SB.

• A logic [0] set the active polling timer to 1.0 ms,

• A logic [1] sets the active polling timer to 55

μs.

VBATP OV

Disable

VBATP Overvoltage protection

• 0 - Enabled

• 1 - Disable

WAKE_B

VDDQ Check

Enable/Disable WAKE_B to wake-up the device on falling edge when VDDQ is not present.

• 0 - WAKE_B is pulled up to VDDQ (internally and/or externally). WAKE_B is ignored while in LPM if VDDQ

is low.

• 1 - WAKE_B is externally pulled up to VBATP or VDDQ and wakes upon a falling edge of the WAKE_B pin

regardless of the VDDQ status.(VDDQ is not expected to go low)

Int_B_Out

Interrupt pin behavior

• 0 - INT pin stays low when interrupt occurs

• 1 - INT pin pulse low and return high

13-12

Aconfig(1-0)

Configure the AMUX output control method

• 00 - SPI (default)

• 01 - SPI

• 10 - HW 2-bit

• 11 - HW 3-bit

Refer to section 7.7, AMUX functional block, page 31 for details on 2 and 3-bit hardwire configuration.

11-0

SP11 - SP0

111_1111_1111

Configure the SP pin as Switch to Battery (SB) or Switch to ground (SG)

• 0 - Switch to Ground

• 1 - Switch to Battery

CD1030 Datasheet(PDF) 39 Page - NXP Semiconductors

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