CD1030 datasheet(4/67 Pages) NXP

4 / 67 page

Analog Integrated Circuit Device Data

NXP Semiconductors

CD1030

Internal block diagram

Figure 2. CD1030 internal block diagram

Wetting (2.0 mA to 20 mA)

Sustain (2.0 mA)

Low Power Mode (1.0 mA)

VBATP

To SPI

SG0

VBATP

4.0 V

reference

To SPI

SP0-7

Internal 2.5 V

VBATP

VDDQ

Inputs

SG0

SG2

SG1

SG20

SP11

SP0

SP1

AMUX

VBATP

VDDQ

GND

SCLK

MOSI

MISO

CS_B

WAKE_B

INT_B

Oscillator

and

Clock control

VBATP, VDDQ

Internal 2.5 V/5.0 V

Power On Reset

Bandgap reference

Sleep Power

Temperature

Monitor and

Control

SPI Interface and

Control

Internal 2.5 V

VDDQ

Mux control

Interrupt

control

VDDQ

125 k

WAKE_B control

VDDQ

125 k

Internal 2.5 V

VBATP

Internal 2.5 V

4.0 V

reference

VBATP

To SPI

SGx

4.0 V

reference

VBATP

To SPI

SG5

4.0 V

reference

SG5

1/6 Ratio

VDDQ

125 k

Wetting (2.0 mA to 20 mA)

Sustain (2.0 mA)

Low Power Mode (1.0 mA)

Wetting (2.0 mA to 20 mA)

Sustain (2.0 mA)

Low Power Mode (1.0 mA)

Wetting (2.0 mA to 20 mA)

Sustain (2.0 mA)

Low Power Mode (1.0 mA)

Wetting (2.0 mA to 20 mA)

Sustain (2.0 mA)

Low Power Mode (2.0 mA)

CD1030 Datasheet(PDF) 4 Page - NXP Semiconductors

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