CD1030 datasheet(49/67 Pages) NXP

49 / 67 page

Analog Integrated Circuit Device Data

NXP Semiconductors

CD1030

7.9.17 Comparator only SP

The comparator only register allows the input comparators to be active during LPM with no polling current. In this case, the inputs can

receive a digital signal on the order of the LPM clock cycle and wake-up on a change of state. This register is intended to be used for

signals that are driven by an external chip and drive to 5.0 V.

7.9.18 Comparator only SG

The comparator only register allows the input comparators to be active during LPM with no polling current. In this case, the inputs can

receive a digital signal on the order of the LPM clock cycle and wake-up on a change of state. This register is intended to be used for

signals driven by an external chip and drive to 5.0 V.

Table 34. Comparator only SP register

R/W

SPI Data Bits [23 - 0]

[31-25]

[24]

bit 23

bit 22

bit 21

bit 20

bit 19

bit 18

bit 17

bit 16

0010_010

0/1

FAULT

STATUS

INTflg

Unused

Default on POR

000000

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

Unused

SP11

SP10

SP9

SP8

00000000

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

00000000

MISO Return Word

bit 23

bit 22

bits [21 - 0]

0010_010[R/W]

FAULT

STATUS

INTflg

Table 35. Comparator only SG register

R/W

SPI data bits [23 - 0]

[31-25]

[24]

bit 23

bit 22

bit 21

bit 20

bit 19

bit 18

bit 17

bit 16

0010_011

0/1

FAULT

STATUS

INTflg

Unused

SG20

SG19

SG18

SG17

SG16

Default on POR

000000

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

SG15

SG14

SG13

SG12

SG11

SG10

SG9

SG8

00000000

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SG7SG6

SG5SG4

SG3SG2

SG1SG0

00000000

MISO Return Word

bit 23

bit 22

bits [21 - 0]

0010_011[R/W]

FAULT

STATUS

INTflg

CD1030 Datasheet(PDF) 49 Page - NXP Semiconductors

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