CD1030 datasheet(42/67 Pages) NXP

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Analog Integrated Circuit Device Data

NXP Semiconductors

CD1030

7.9.7

Wetting current level SG register 0

Three bits are used to control the configurable wetting currents for each individual input pin with the values set in the Table 22. The default

configuration is 16 mA for all channels. The MCU may change or update the wetting current register via software at any time in Normal

mode.

See Table 25 for the selectable wetting current level values for both SPx and SGx pins.

7.9.8

Wetting current level SG register 1

Three bits are used to control the configurable wetting currents for each individual input pin with the values set in the Table 23. The default

configuration is 16 mA for all channels. The MCU may change or update the wetting current register via software at any time in Normal

mode.

See Table 25 for the selectable wetting current level values for both SPx and SGx pins.

Table 22. Wetting current level SG register 0

R/W

SPI data bits [23 - 0]

[31-25]

[24]

bit [23 - 21]

bit [20 - 18]

bit [17 - 16]

0000_101

0/1

SG7 [2-0]

SG6[2-0]

SG5[2-1]

Default on POR

110

bit [15]

bit [14 - 12]

bit [11 - 9]

bit [8]

SG5[0]

SG4 [2-0]

SG3[2-0]

SG2[2]

110

bit [7 - 6]

bit [5 - 3]

bit [2 - 0]

SG2[1-0]

SG1[2-0]

SG0[2-0]

110

MISO Return Word

bits [23 - 0]

0000_101[R/W]

Table 23. Wetting current level SG register 1

R/W

SPI data bits [23 - 0]

[31-25]

[24]

bit [23 - 21]

bit [20 - 18]

bit [17 - 16]

0000_110

0/1

SG15[2-0]

SG14[2-0]

SG13[2-1]

Default on POR

110

bit [15]

bit [14 - 12]

bit [11 - 9]

bit [8]

SG13[0]

SG12 [2-0]

SG11[2-0]

SG10[2]

110

bit [7 - 6]

bit [5 - 3]

bit [2 - 0]

SG10[1-0]

SG9[2-0]

SG8[2-0]

110

MISO Return Word

bits [23 - 0]

0000_110[R/W]

CD1030 Datasheet(PDF) 42 Page - NXP Semiconductors

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