LTC3613 datasheet(32/44 Pages) AD

32 / 44 page

LTC7131-1

Rev. 0

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APPLICATIONS INFORMATION

IGATECHG = f(QT + QB), where QT and QB are the gate

charges of the internal top and bottom power MOSFETs

and f is the switching frequency. Since INTVCC is a low

dropout regulator output powered by SVIN, its power

loss equals to Equation 24.

PLDO = SVIN • IINTVCC

(24)

3. Other “hidden” losses such as transition loss and cop-

per trace and internal load resistances can account for

additional efficiency degradations in the overall power

system. It is very important to include these “system”

level losses in the design of a system. Transition loss

arises from the brief amount of time the top power

MOSFET spends in the saturated region during switch

node transitions. Other losses including diode conduc-

tion losses during dead-time and inductor core losses

which generally account for less than 2% total addi-

tional loss.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 20. Check the following in the

PC layout:

1. The INTVCC decoupling capacitor should be placed

immediately adjacent to the IC between the INTVCC pin

and PGND plane. A 1µF ceramic capacitor of the X7R

or X5R type is small enough to fit very close to the IC

to minimize the ill effects of the large current pulses

drawn to drive the bottom MOSFETs. An additional

4.7µF to 10µF of ceramic, tantalum or other very low

ESR capacitance is recommended in order to keep the

internal IC supply quiet.

2. Connect the remote sense pins, VSENSE+ and VSENSE–,

directly to the point where maximum VOUT accuracy

is desired. The two traces should be routed as close

together as possible.

3. Do the (+) plates of CIN connect to the drain of the

topside MOSFET as closely as possible? This capac-

itor provides the pulsed current to the MOSFET.

4. Keep the switching nodes, SW, BOOST away from

sensitive small-signal nodes (REF, DAOUT, VSENSE+,

VSENSE–, FB). Ideally the SW, and BOOST printed cir-

cuit traces should be routed away and separated from

the IC and especially the quiet side of the IC. Separate

the high dv/dt traces from sensitive small-signal nodes

with ground traces or ground planes.

5. Use a low impedance source such as a logic gate to

drive the MODE/SYNC pin and keep the lead as short

as possible.

6. Figure 20 illustrates all branch currents in a switch-

ing regulator. It becomes very clear after studying the

current waveforms why it is critical to keep the high

switching current paths to a small physical size. High

electric and magnetic fields will radiate from these

Figure 20. Branch Current Waveforms

RIN

VIN

VOUT

CIN

COUT

SW2

SW1

DCR

7131-1 F20

BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH

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