LTC3613 datasheet(11/44 Pages) AD

11 / 44 page

LTC7131-1

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

PGLIM (Pin C2): PGOOD Threshold Programming Pin.

The voltage difference ΔV between this pin and SGND sets

the VOUT overvoltage threshold to VREF + 0.4 • ΔV and the

undervoltage threshold to VREF – 0.4 • ΔV. Tying this pin

to INTVCC sets the threshold to its default value of ±10%.

SGND (Pins C3, C4): Signal Ground. Reference setting

resistor, slew rate control capacitor, and frequency setting

resistor connections should return to SGND. For optimum

load regulation, the SGND pin should be kelvin-connected

to the PCB location between the negative terminals of the

output capacitors and should not be connected through

the PGND plane.

PGOOD (Pin C5): Power Good. This open-drain output is

pulled down to SGND on start-up and while the output volt-

age is outside the power good window set by the PGLIM

pin. If the output voltage increases and stays inside the

power good window for more than the delay programmed

at the PGFD pin, the PGOOD pin is released. If the output

voltage leaves the power good window for more than 16

switching cycles the PGOOD pin is pulled down.

PGFD (Pin C6): PGOOD Deglitch Filter Delay Select. The

voltage at this pin sets the delay that the output must be

in regulation before the PGOOD flag is asserted. The delay

can be programmed to one of eight discrete values where

tDELAY = 200μs • 2N (N = 0 to 7).

ASEL (Pin D1): Serial Bus Address Configuration Input.

Connect a ±1% resistor from this pin to ground in order

to select the 4 LSBs of the serial bus interface address.

(See Table 5).

MARGIN (Pin D2): Fast Margining Select. In the default

mode when this pin is floating, the reference voltage

margin offset is changed with MFR_VOUT_COMMAND

through the serial interface. If this pin is pulled high, the

reference voltage margin offset is immediately ramped to

the value pre-stored in the MFR_VOUT_MARGIN_HIGH

gin offset is immediately ramped to the value pre-stored

in MFR_VOUT_MARGIN_LOW register.

WP (Pin D3): Write Protect Pin. An internal 10µA current

source pulls the pin to 3.3V. If WP is high, the PMBus

writes are restricted.

SCL (Pin D4): Serial Bus Clock Input. A pull-up resistor

is required in the application.

SDA (Pin D5): Serial Bus Data Input and Output. A pull-up

resistor is required in the application.

CLKOUT (Pin D6): Clock Out Signal for 2-Phase Operation.

The phase of this clock is 180° with respect to the internal

clock. Signal swing is from INTVCC to GND.

BOOST (Pin D7): Boosted Floating Driver Supplies. The

(+) terminal of the booststrap capacitors connect to these

pins. These pins swing from a diode voltage drop below

INTVCC up to VIN + INTVCC.

GND (Pins E1, E2, E3, E4, F1, F2, F3, F4, G1, G2, G3,

G4): Power Ground. Must be soldered to PCB for electrical

connection and rated thermal performance.

ALERT (Pin E5): Open Drain Digital Output. Connect the

system SMBALERT interrupt signal to this pin. A pull-up

resistor is required in the application.

SW (Pins E6, E7, F5, F6, F7, G5, G6, G7, H5, H6,

H7, J5, J6, J7): Switching Node. This pin connects to

the drains of the internal main and synchronous power

MOSFET switches.

VIN (Pins H1, H2, H3, H4, J1, J2, J3, J4): Power Input

Supply. VIN connects to the drain of the internal N-channel

power MOSFET. This pin is independent of SVIN and may

be connected to the same voltage or to a lower voltage

supply.

LTC3613 Datasheet(PDF) 11 Page - Analog Devices

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