LTC3613 datasheet(27/44 Pages) AD

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LTC7131-1

Rev. 0

For more information www.analog.com

(a) PGOOD Window Set to ±10% Default

LTC7131-1

INTVCC

RREF = R1 + R2

REF

7131-1 F15a

PGLIM

LTC7131-1

INTVCC

REF

7131-1 F15b

PGLIM

(b) PGOOD Window Set by R1/R2

Figure 15. PGOOD Window

APPLICATIONS INFORMATION

Output Voltage Programming

The output voltage is set by an external resistor according

to Equation 13.

VOUT = 100µA • RREF

(13)

where RREF is the total resistance between REF pin and

SGND. A capacitor (0.1µF max) connected from REF to

SGND is recommended for noise filtering. For accurate

PGOOD reporting at startup, choose CREF < 10CSS.

Programming PGOOD Threshold and Filter Delay

The upper and lower Power Good threshold default

to ±10% when the PGLIM pin is tied to INTVCC (see

Figure 15a). However, if a narrower or wider window

is desired, these windows can be programmed to any

desired value in the range of 5% to 40%.

The PGOOD upper/lower threshold is programmed by

replacing the single resistor on the REF pin with a resistor

divider as follows (see Figure 15b):

Reference Voltage = 100µA • (R1+R2)

PGOOD Window = ±40% • R2/(R1+R2)

The PGOOD window is always centered on the DAC

adjusted reference voltage, thus the center will move to

the new reference voltage when margined up or down.

The falling PGOOD (power good to power bad) is filtered

and delayed by 16 clock cycles, thus giving the loop 16

switching cycles to recover from the power bad condition

before pulling the PGOOD pin low.

The rising PGOOD (power bad to power good) filter delay

is user programmable by a configuration resistor at the

PGFD pin and is programmable to one of 8 possible delays

from 200μs to 25.6ms as shown in Table 6. Minimum

delay of 200μs can be set by grounding the PGLIM pin

and maximum delay of 25.6ms can be set by tying PGLIM

to INTVCC.

The PGFD pin is sampled only at power on and at initial-

ization after the rising edge of RUN_MSTR, RUN_STBY

or the OPERATION register ON bit. Changes to PGFD will

not take effect until one of these events occur.

Table 6. PGFD Resistor Selection

PGFD RESISTOR

PGOOD DELAY

0Ω

200μs

28kΩ

400μs

46.4kΩ

800μs

64.9kΩ

1.6ms

84.5kΩ

3.2ms

102kΩ

6.4ms

121kΩ

12.8ms

Open or Short to INTVCC

25.6ms

Address Selection (ASEL pin)

The LTC7131-1 slave address is selected by the ASEL pin.

The upper four bits of the address are hardwired inter-

nally to 0100 and the lower three bits are programmed by

a resistor connected between the ASEL and SGND (see

Table 7). This allows up to 8 different LTC7131-1’s on

a single board. The LTC7131-1 will also respond to the

Global Address 0x5A and the 7-bit address stored in the

MFR_RAIL_ADDRESS register.

The ASEL pin is sampled only at power on and at initial-

ization after the rising edge of RUN_MSTR, RUN_STBY

or OPERATION register ON bit. Changes to ASEL will not

take affect until one of these events occur.

LTC3613 Datasheet(PDF) 27 Page - Analog Devices

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