LTC3613 datasheet(28/44 Pages) AD

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LTC7131-1

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Table 7. ASEL Resistor Selection

ASEL RESISTOR

SLAVE ADDRESS

0Ω

0100000

28kΩ

0100001

46.4kΩ

0100010

64.9kΩ

0100011

84.5kΩ

0100100

102kΩ

0100101

121kΩ

0100110

Open or short to INTVCC

0100111

Margining/CSLEW Selection/Margin Pin

Writing to the MFR_VOUT_COMMAND register via the

PMBus allows the adjustment of the VOUT reference up to

±25% around the voltage at the REF pin. This voltage can

be adjusted in 0.1% increments by writing the appropriate

9-bit two’s complement value to the register. The MFR_

VOUT_MARGIN_HIGH and MFR_VOUT_MARGIN_LOW

value by selecting the desired register with the MARGIN

pin or the OPERATION command as specified in Table 8.

Table 8. VOUT Margining with the MARGIN Pin and OPERATION

Command

MARGIN

OPERATION

BITS [5:4]

VOUT REFERENCE

BIT 5 BIT 4

<0.4V

= [1 + MFR_VOUT_MARGIN_LOW(%) ] • VREF

>1.2V

= [1 + MFR_VOUT_MARGIN_HIGH(%) ] • VREF

Hi-Z

= [1 + MFR_VOUT_COMMAND(%) ] • VREF

Hi-Z

= [1 + MFR_VOUT_MARGIN_LOW(%) ] • VREF

Hi-Z

= [1 + MFR_VOUT_MARGIN_HIGH(%) ] • VREF

Hi-Z

= [1 + MFR_VOUT_COMMAND(%) ] • VREF

* Setting both bits 4 and 5 high at the same time is illegal and will be

ignored.

Pre-loading the registers and using the MARGIN pin pro-

vides fast margining by eliminating the latency inherent to

serial bus communication. Once the registers are loaded

the output voltage change is limited only by the loop band-

width and the slew rate capacitor (CSLEW).

The CSLEW pin provides slew rate limiting during reference

voltage changes. When the reference is changed by either

the MARGIN pin, OPERATION command, or writing new

values to the register, the LTC7131-1 counts up or down

from the current value in the register to the new value

at 0.1% per step. The step duration is set by the CSLEW

capacitor. The slew rate during the transition is given by

Equation 14.

SR =

0.1

CSLEW(nF)+0.0043

% / ms

(14)

If the CSLEW pin is left open, SR defaults to 23%/ms. The

slew rate limit can be disabled if desired by tying the CSLEW

pin to INTVCC. When disabled, the reference is immedi-

ately stepped from old value to new value in <100ns.

Differential Amplifier

The LTC7131-1 has true remote voltage sense capability.

The sense connections, VSENSE+ and VSENSE–, should be

returned from the load, back to the differential amplifi-

er’s inputs through a common, tightly coupled pair of

PC traces. The differential amplifier rejects common

mode signals capacitively or inductively radiated into the

feedback PC traces as well as ground loop disturbances.

However, it is still important to avoid routing these sen-

sitive traces near any high speed switching nodes in the

circuit. Ideally, the VSENSE+ and VSENSE– traces should be

shielded by a low impedance ground plane to maintain

signal integrity.

The LTC7131-1 differential amplifier has 160kΩ input

impedance on VSENSE+. It is designed to be connected

directly to the output. The output of the differential

amplifier, DAOUT, connects to the FB pin to set the output

voltage.

Soft-Start

After the LTC7131-1 is turned on or power applied and

finishes its ~500µs initialization sequence, the chip enters

a soft start-up state. The type of soft startup behavior is

set by the TRACK/SS pin:

1. Floating the TRACK/SS selects the internal soft-start

circuit. This circuit ramps the output voltage to the final

value within 1ms.

2. If a longer soft-start period is desired, it can be set

externally with a capacitor on the TRACK/SS pin.

The TRACK/SS pin reduces the value of the internal

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