SC18IM704 datasheet(11/28 Pages) NXP

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NXP Semiconductors

SC18IM704

UART to I2C-bus bridge

002aab883

VSS

pin latch data

GPIO pin

glitch rejection

input data

Figure 15. Open-drain output configuration

9.2.3 Programmable I/O pins state register (IOState)

When read, this register returns the actual state of all I/O pins. When written, each

Bit

Symbol

Description

7:0

IOLevel

Set the logic level on the output pins.

Write to this register:

logic 0 = set output pin to zero

logic 1 = set output pin to one

Read this register returns states of all pins.

Table 7. IOState - Programmable I/O pins state register (address 0x04h) bit

description

9.2.4 I2C-bus address register (I2CAdr)

The contents of the register represents the device’s own I2C-bus address. The most

significant bit corresponds to the first bit received from the I2C-bus after a START

condition. A logic 1 in I2CAdr corresponds to a HIGH level on the I2C-bus, and a logic

0 corresponds to a LOW level on the I2C-bus. The least significant bit is not used, but

should be programmed with a ‘0’.

I2CAdr is not needed for device operation, but should be configured so that its address

does not conflict with an I2C-bus device address used by the bus controller.

9.2.5 I2C-bus clock rates (I2CClk)

This register determines the serial clock frequency. The various serial rates are shown in

Table 8. The frequency can be determined using the following formula:

I2CClk (I2CClkH +

I2CClkL)

I2C-bus clock frequency

5 (minimum)

375 kHz

268 kHz

208 kHz

99 kHz

Table 8. I2C-bus clock frequency

SC18IM704

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Product data sheet

Rev. 1.0 — 22 September 2021

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