SC18IM704 datasheet(12/28 Pages) NXP

12 / 28 page

NXP Semiconductors

SC18IM704

UART to I2C-bus bridge

I2CClk (I2CClkH +

I2CClkL)

I2C-bus clock frequency

255

7.4 kHz

Table 8. I2C-bus clock frequency...continued

Remark: I2CClk is the 16-bit number formed by I2CClkH : I2CClkL.

Caution: The upper 8-bit portion will rarely be used as the I2C baud rate will be very

slow.

9.2.6 I2C-bus time-out (I2CTO)

The time-out register is used to determine the maximum time that SCL is allowed to be

LOW before the I2C-bus state machine is reset.

When the I2C-bus interface is running, I2CTO is loaded after each I2C-bus state

transition.

Bit

Symbol

Description

7:1

TO[7:1]

time-out value

enable/disable time-out function

logic 0 = disable

logic 1 = enable

Table 9. I2CTO - I2C-bus time-out register (address 0x09h) bit description

The least significant bit of I2CTO (TE bit) is used as a time-out enable/disable. A logic 1

will enable the time-out function. The time-out period can be calculated as follows:

The time-out value may vary, and it is an approximate value.

I2CClock is the register value from Section 9.2.5 "I2C-bus clock rates (I2CClk)".

9.2.7 I2C-bus status register (I2CStat)

This register reports the I2C-bus transmit and receive frame status, whether the frame

transmits correctly or not.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I2C-bus status description

I2C_OK

I2C_NACK_ON_ADDRESS

I2C_NACK_ON_DATA

I2C_TIME_OUT

Table 10. I2C-bus status

SC18IM704

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 22 September 2021

12 / 28

SC18IM704 Datasheet(PDF) 12 Page - NXP Semiconductors

SC18IM704 Datasheet(HTML) 12 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL