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LPC804 Datasheet(PDF) 7 Page - NXP Semiconductors |
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LPC804 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 89 page  LPC804 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2021. All rights reserved. Product data sheet Rev. 2.0 — 21 September 2021 7 of 87 NXP Semiconductors LPC804 32-bit Arm Cortex-M0+ microcontroller 6. Block diagram Fig 4. LPC804 block diagram aaa-029233 CLKOUT Vdd CLKIN ISP Access Port RESET Clock Generation, Power Control, and other System Functions Voltage Regulator DEBUG INTERFACE IOP bus GPIOs GPIOs AND GPOINT Flash interface Flash 32 kB Multilayer AHB Matrix AHB to APB bridge T0 Match/ Capture P0 M0 P1 P2 COMP Inputs ADC inputs and Triggers GPIOs UART0,1 SPI0 I2C0,1 APB slave group LPOSc Windowed WDT ARM Cortex M0+ System control IOCON Registers CTIMER0 UART 0 and 1 SPI0 I2C 0 and 1 Periph Input Mux Selects Comparator PMU Registers 12-bit ADC Switch Matrix Wakeup Timer Multi-Rate Timer Boot ROM 8 kB SRAM 4 kB CAPT Capacitive Touch 10-bit DAC DAC outputs PLU PLU |
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