RT600 datasheet(160/167 Pages) NXP

160 / 167 page

RT600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.0 — 1 April 2022

160 of 165

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

RT600 v.1.8

20211209

Product data sheet

1.7

• Updated SWCLK resistor for PIO2_25 and description for PIO0_29 (Function 1) in

Table 4 “Pin description”.

• Updated Section 14.12 “High Speed SPI Interface (Flexcomm Interface 14)”.

• Updated footnote [3] in Section 13.1 “General operating conditions”.

• Added Fail Safe Pad and High Speed Pad details in Table 5 “Power Supply for pins”

• Removed below footnotes from Section 14.8 “I2C-bus”:

a. The maximum fall time for the SDA output stage tf is specified at 250 ns. This

allows series protection resistors to be connected in between the SDA and the SCL

pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

b. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster

fall times are allowed.

c. In Fast-mode Plus, fall time is specified the same for both output stage and bus

timing. If series resistors are used, designers should allow for this when considering

bus timing.

• Removed field MIMXRT633SFVKB and MIMXRT633SFAWBR from Section 4

“Ordering information”.

• Updated Section 9 “Termination of unused pins” and Section 16.4 “RTC oscillator”.

• Section 10.20.1 “12-bit Analog-to-Digital Converter (ADC)” updated to read ADC runs

up to 1Msamples/s.

• ADC functional description updated in Section 10.20.1.1 “Features”.

• Added minimum reset pulse width 4ns inTable 4 “Pin description”.

• Updated I2C Bus fall time details in Section 13.5 “Pin characteristics”.

• VDDCORE voltage is set to 0.7 note added in Table 28 “Static characteristics:

Power consumption in deep-sleep mode[4]”

• Added PLL lock time is approximately 150 us in Section 10.13.2 “System PLL (PLL0)”.

• Added only FBB must be used for active mode and only RBB must be used for deep

sleep mode in Section 10.14 “Power control”.

• In Figure 30 “Current measurements for memory partition”, Y-axis changed from

VDD1V8 Current (mA) to VDDCORE Current (mA) and also, added that internal LDO

is disabled in the second bullet.

• Added Section 16.7 “Boundary Scan Mode” and Section 16.8 “VDDA_BIAS Power

Supply Connection”.

• Replaced “VDD_BIAS must be connected to the highest VDDIO rail voltage used for

the ADC input channel or comparator inputs” to “VDD_BIAS must be equal to max

ADC input voltage or max comparator input voltage” in Table 4 “Pin description”, Table

18 “Limiting values”. Table 20 “General operating conditions”, and Table 21 “General

operating conditions”.

• In Section 7 “Pinning information” updated all GPIO pins are fail safe up to 3.6V when

VDDIO supply is 0V except pins PIO1_18 (instead of PIO1_19) to PIO1_31.

• Added practical range of crystal frequencies for PLL usage is 5 MHz to 26 MHz in

Section 10.13.1.4 “Crystal oscillator”.

Table 57.

Revision history …continued

Document ID

Release date Data sheet status

Change notice Supersedes

RT600 Datasheet(PDF) 160 Page - NXP Semiconductors

RT600 Datasheet(HTML) 160 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL