MAX5083ATE datasheet(12/18 Pages) MAXIM

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The allowable deviation of the output voltage during fast

load transients also determines the output capacitance,

its ESR, and its equivalent series inductance (ESL).

The output capacitor supplies the load current during

a load step until the controller responds with a greater

duty cycle. The response time (tRESPONSE) depends

on the closed-loop bandwidth of the converter (see the

Compensation Design section). The resistive drop across

the output capacitor’s ESR, the drop across the capaci-

tor’s ESL (ΔVESL), and the capacitor discharge causes

a voltage droop during the loadstep. Use a combination

of low-ESR tantalum/aluminum electrolyte and ceramic

capacitors for better transient load and voltage ripple

performance. Nonleaded capacitors and capacitors in

parallel help reduce the ESL. Keep the maximum output

voltage deviation below the tolerable limits of the elec-

tronics being powered. Use the following equations to

calculate the required ESR, ESL, and capacitance value

during a load step:

ESR

STEP

RESPONSE

OUT

ESL

STEP

ESR

ESL

∆

where ISTEP is the load step, tSTEP is the rise time of the

load step, and tRESPONSE is the response time of the

controller.

Compensation Design

The MAX5082/MAX5083 use a voltage-mode control

scheme that regulates the output voltage by comparing

the error amplifier output (COMP) with an internal ramp

to produce the required duty cycle. The output lowpass

LC filter creates a double pole at the resonant frequency,

which has a gain drop of -40dB/decade. The error ampli-

fier must compensate for this gain drop and phase shift to

achieve a stable closed-loop system.

The basic regulator loop consists of a power modulator,

an output feedback divider, and a voltage-error amplifier.

The power modulator has a DC gain set by VIN/VRAMP,

with a double pole and a single zero set by the output

inductance (L), the output capacitance (COUT) (C5 in

the Typical Application Circuit) and its equivalent series

resistance (ESR). The power modulator incorporates a

voltage feed-forward feature, which automatically adjusts

for variations in the input voltage resulting in a DC gain of

10. The following equations define the power modulator:

MOD(DC)

RAMP

OUT

ZESR

OUT

2 LC

ESR

π×

The switching frequency is internally set at 250kHz or can

vary from 150kHz to 350kHz when driven with an external

SYNC signal. The crossover frequency (fC), which is the

frequency when the closed-loop gain is equal to unity,

should be set at 15kHz or below therefore:

fC ≤ 15kHz

The error amplifier must provide a gain and phase bump

to compensate for the rapid gain and phase loss from the

LC double pole. This is accomplished by utilizing a type 3

compensator that introduces two zeroes and 3 poles into

the control loop. The error amplifier has a low-frequency

pole (fP1) near the origin.

The two zeros are at:

and f

R5 C7

(R6 R3) C6

π×

and the higher frequency poles are at:

and f

R6 C6

C7 C8

π×





π×

× 



Compensation When fC < fZESR

Figure 3 shows the error amplifier feedback as well as its

gain response for circuits that use low-ESR output capaci-

tors (ceramic). In this case fZESR occurs after fC.

fZ1 is set to 0.8 x fLC(MOD) and fZ2 is set to fLC to

compensate for the gain and phase loss due to the

double pole. Choose the inductor (L) and output capacitor

(COUT) as described in the Inductor and Output Capacitor

Selection section.

MAX5082/MAX5083

1.5A, 40V, MAXPower Step-Down

DC-DC Converters

www.maximintegrated.com

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