ADPD6000 datasheet(66/89 Pages) AD

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Data Sheet

ADPD6000

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Rev. 0 | 66 of 89

Table 21. Register Details

Reg

Name

Bits

Bit Name

Description

Reset Access

0x000A OSC32M_CAL

OSC_32M_CAL_START

Start high frequency oscillator calibration cycle. Writing a 1 to

this bit causes the high frequency oscillator calibration cycle

to occur. 32 MHz oscillator cycles are counted during 128 low

frequency oscillator cycles if using the 1 MHz low frequency

oscillator, or 4 low frequency oscillator cycles if using the

32 kHz low frequency oscillator. The OSC_32M_CAL_COUNT

bits are updated with the count. The calibration circuit clears

the OSC_32M_CAL_START bit when the calibration cycle is

completed. Silicon Version 0 counts 32 low frequency oscillator

cycles if using the 32 kHz low frequency oscillator.

0x0

R/W

[14:0]

OSC_32M_CAL_COUNT

High frequency oscillator calibration count. These bits contain

the total number of 32 MHz cycles that occurred during the last

high frequency oscillator calibration cycle.

0x0

0x000B OSC960K

CAPTURE_TIMESTAMP

Enable time stamp capture. This bit field is used to activate the

time stamp capture function. When set, the next rising edge on

the time stamp input (defaults to GPIO0) causes a time stamp

capture. This bit is cleared when the time stamp occurs.

0x0

R/W

[14:11]

RESERVED

Reserved.

0x0

OSC_CAL_ENABLE

Enable clock calibration clocking. Writing a 1 to this bit enables

the clocking of the low frequency and high frequency calibration

circuits.

0x0

R/W

[9:0]

OSC_960K_FREQ_ADJ

Low frequency oscillator frequency control. 0x000 is the lowest

frequency, and 0x3FF is maximum frequency.

0x2B2 R/W

0x000D TS_FREQ

[15:0]

TIMESLOT_PERIOD_L

Lower 16 bits of time slot period in low frequency

oscillator cycles. The time slot rate is (timer clock frequency)/

(TIMESLOT_PERIOD_x). The default value operates at 100 Hz

when using the 960 kHz clock. If the timer clock is set as

an external source from the GPIO, either 960 kHz or 32 kHz,

TM_CLK_GPIO_SEL must be configured to match the real clock

frequency.

0x258

R/W

0x000E TS_FREQH

[15:7]

RESERVED

Reserved.

0x0

[6:0]

TIMESLOT_PERIOD_H

Upper seven bits of time slot period in low frequency

oscillator cycles. The time slot rate is (timer clock frequency)/

(TIMESLOT_PERIOD_x). The default value operates at 100 Hz

when using the 960 kHz clock. If the timer clock is set to be

an external source from the GPIO, either 960 kHz or 32 kHz,

TM_CLK_GPIO_SEL must be configured to match the real clock

frequency.

0x0

R/W

0x000F SYS_CTL

SW_RESET

Software Reset. Write 1 to this bit to assert a software reset.

This resets the chip to its default values and stops all AFE

operations. The software reset does not reset the SPI (or

optional I2C) port.

0x0

R0/W

[14:11]

RESERVED

Reserved.

0x0

[10:8]

ALT_CLOCKS

External clock select.

0x0

R/W

000: use internal clocks.

001: use GPIO for low frequency oscillator (960 kHz). Timer

clock also uses this as the source.

010: use GPIO for high frequency oscillator (32 MHz).

011: use GPIO for high frequency oscillator (32 MHz), and

generate low frequency oscillator (1 MHz) from high frequency

oscillator. This feature must be disabled when the ECG is

enabled.

100: use GPIO for timer clock, 32 kHz or 960 kHz.

[7:6]

ALT_CLK_GPIO

Alternate clock GPIO select.

0x0

R/W

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