ADSP-SC591 datasheet(76/145 Pages) AD

76 / 145 page

Rev. A

Page 76 of 145

April 2022

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

Clock and Reset Timing

Table 42 and Figure 10 describe clock and reset operations related to the CGU and RCU. Per the CCLK, SYSCLK, SCLKx, DCLK, and

OCLK timing specifications in Table 26 (Clock Operating Conditions), combinations of SYS_CLKIN0, SYS_CLKIN1, and clock multipli-

ers must not select clock rates in excess of the maximum instruction rate of the processor.

Dynamic Memory Controller (DMC)—Clock, Control, Write and Read Cycle Timing

The DMC clock, control, write and read timings comply with the JEDEC standards. To ensure proper operation of the DDR3/3L, all

DDR3/3L guidelines must be strictly followed. See ADSP-2159x/SC59x Board Design Guidelines for Dynamic Memory Controller (EE-

434).

Table 42. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

fCKIN

SYS_CLKINx Frequency (Crystal)1, 2

1 Applies to PLL bypass mode and PLL nonbypass mode.

2 The tCKIN period (see Figure 10) equals 1/fCKIN.

MHz

SYS_CLKINx Frequency (External SYS_CLKINx)1, 2

MHz

tCKINL

SYS_CLKINx Low Pulse1

16.67

tCKINH

SYS_CLKINx High Pulse1

16.67

tWRST

RESET Asserted Pulse Width Low3

3 Applies after power-up sequence is complete. See Table 41 and Figure 8 for power-up reset timing.

11 × tCKIN

Figure 10. Clock and Reset Timing

SYS_CLKIN0/1

tWRST

tCKIN

tCKINL

tCKINH

SYS_HWRST

ADSP-SC591 Datasheet(PDF) 76 Page - Analog Devices

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