ADSP-SC591 datasheet(19/145 Pages) AD

19 / 145 page

Rev. A

Page 19 of 145

April 2022

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

Each timer can also be started and stopped by any trigger gener-

ator without core intervention. While the ADSP-21591 and

ADSP-21593 processors feature 16 GP timers, timer units TIM-

ER10-TIMER15 have no external pins and can only be

configured for internal modes of operation.

Watchdog Timer (WDT)

Three on-chip software watchdog timers (WDT) can be used by

the Arm Cortex-A5 and/or SHARC+ cores. A software watch-

dog can improve system availability by forcing the processors to

a known state, via a general-purpose interrupt, or a fault, if the

timer expires before being reset by software.

The programmer initializes the count value of the timer, enables

the appropriate interrupt, then enables the timer. Thereafter,

the software must reload the counter before it counts down to

zero from the programmed value, protecting the system from

remaining in an unknown state where software that normally

resets the timer stops running due to an external noise condi-

tion or software error.

General-Purpose Counters (CNT)

A 32-bit general-purpose counter (CNT) is provided that can

operate in general-purpose up/down count modes and can

sense 2-bit quadrature or binary codes as typically emitted by

industrial drives or manual thumbwheels. Count direction is

controlled by a level-sensitive input pin or by two edge

detectors.

A third counter input can provide flexible zero marker support

and can input the push button signal of thumbwheel devices. All

three CNT0 pins have a programmable debouncing circuit.

Internal signals forwarded to a GP timer enable the timer to

measure the intervals between count events. Boundary registers

enable auto-zero operation or simple system warning by inter-

rupts when programmed count values are exceeded.

Housekeeping Analog-to-Digital Converter (HADC)

The housekeeping analog-to-digital converter (HADC) pro-

vides a general-purpose, multichannel, successive

approximation ADC. The following baseline HADC features

apply to all models:

• 12-bit ADC core with built in sample and hold

• Throughput rates up to 1 MSPS

• Single external reference with analog inputs between

0 V and 1.8 V

• Selectable ADC clock frequency including the ability to

program a prescaler

• Adaptable conversion type; allows single or continuous

conversion with option of autoscan

• Four single-ended input channels

• Autosequencing capability with up to four autoconversions

in a single session. Each conversion can be programmed to

select one to four input channels.

• Four data registers (individually addressable) to store con-

version values

For the ADSP-SC592 and ADSP-SC594 processors, the follow-

ing features extend the baseline features above:

• Total of eight single-ended input channels that can be fur-

ther extended to 15 channels by adding an external channel

multiplexer

• Autosequencing capability with up to a total of eight auto-

conversions in a single session. Each conversion can be

programmed to select one to fifteen input channels.

• 16 data registers (individually addressable) to store conver-

sion values

USB 2.0 High Speed (HS) On the Go (OTG) Controller

The USB supports high speed/full speed/low speed (HS/FS/LS)

USB2.0 on the go (OTG) and UTMI+ low pin interface (USBC).

The USB 2.0 OTG dual-role device controller provides a low

cost connectivity solution in industrial applications, as well as

consumer mobile devices such as cell phones, digital still

cameras, and MP3 players. The USB 2.0 controller allows these

devices to transfer data using a point to point USB connection

without the need for a PC host. The module can operate in a tra-

ditional USB peripheral only mode as well as the host mode

presented in the OTG supplement to the USB 2.0 specification.

The USB controller does not have an integrated on-chip PHY

and must connect to an external PHY on the board through an

USBC 8-bit interface supported by the USB controller.

Media Local Bus (MediaLB)

The automotive model has a Microchip MediaLB (MLB) device

interface that allows the processors to function as a media local

bus device. It includes support for both 3-pin and 6-pin media

local bus protocols. The MLB 3-pin configuration supports

speeds up to 1024 × FS. The MLB 6-pin configuration supports

speed of 2048 × FS. The MLB also supports up to 64 logical

channels with up to 468 bytes of data per MLB frame.

The MLB interface supports MOST25, MOST50, and MOST150

data rates and operates in device mode only.

2-Wire Controller Interface (TWI)

The processors include six 2-wire interface (TWI) modules that

provide a simple exchange method of control data between mul-

tiple devices. The TWI module is compatible with the widely

used I2C bus standard. The TWI module offers the capabilities

of simultaneous controller and target operation and support for

both 7-bit addressing and multimedia data arbitration. The

TWI interface utilizes two pins for transferring clock

(TWI_SCL) and data (TWI_SDA) and supports the protocol at

speeds up to 400 kbps. The TWI interface pins are compatible

with 3.3 V logic levels.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

ADSP-SC591 Datasheet(PDF) 19 Page - Analog Devices

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