ADSP-SC591 datasheet(83/145 Pages) AD

83 / 145 page

Rev. A

Page 83 of 145

April 2022

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

Table 48. SPORTs—Internal Clock1

Parameter

Min

Max

Unit

Timing Requirements

tSFSI

Frame Sync Setup Before SPTx_CLK

(Externally Generated Frame Sync in Either Transmit or

Receive Mode)2

tHFSI

Frame Sync Hold After SPTx_CLK

(Externally Generated Frame Sync in Either Transmit or

Receive Mode)2

–0.5

tSDRI

Receive Data Setup Before SPTx_CLK2

3.4

tHDRI

Receive Data Hold After SPTx_CLK2

3.6

Switching Characteristics

tDFSI

Frame Sync Delay After SPTx_CLK (Internally Generated

Frame Sync in Transmit or Receive Mode)3

3.5

tHOFSI

Frame Sync Hold After SPTx_CLK (Internally Generated

Frame Sync in Transmit or Receive Mode)3

–3

tDDTI

Transmit Data Delay After SPTx_CLK3

3.5

tHDTI

Transmit Data Hold After SPTx_CLK3

–3

tSPTCLKIW

SPTx_CLK Width4

0.5 × tSPTCLKPROG – 1.5

tSPTCLKW

SPTx_CLK Period4

tSPTCLKPROG – 1.5

1 Specifications apply to all four SPORTs.

2 Referenced to the sample edge.

3 Referenced to drive edge.

4 See Table 26 for details on the minimum period that can be programmed for fSPTCLKPROG.

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