ADSP-SC591 datasheet(92/145 Pages) AD

92 / 145 page

Rev. A

Page 92 of 145

April 2022

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

SPI Port—Slave Timing

SPI0, SPI1, SPI2, and SPI3

Table 55 and Figure 22 describe SPI port slave operations. Note that

• In dual-mode data transmit, the SPIx_MOSI signal is also an output.

• In quad-mode data transmit, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are also outputs.

• In dual-mode data receive, the SPIx_MISO signal is also an input.

• In quad-mode data receive, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are also inputs.

• In SPI slave mode, the SPI clock is supplied externally and is called fSPICLKEXT:

• Quad mode is supported by SPI1 and SPI2.

• CPHA is a configuration bit in the SPI_CTL register.

Table 55. SPI Port—Slave Timing1

1 All specifications apply to SPI0, SPI1, SPI2, and SPI3.

Parameter

Min

Max

Unit

Timing Requirements

tSPICHS

SPIx_CLK High Period2

2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPIx_CLK. For the external

SPIx_CLK ideal maximum frequency, see the fSPICLKTEXT specification in Table 26.

0.5 × tSPICLKEXT – 1.5

tSPICLS

SPIx_CLK Low Period2

0.5 × tSPICLKEXT – 1.5

tSPICLK

SPIx_CLK Period2

tSPICLKEXT – 1.5

tHDS

Last SPIx_CLK Edge to SPIx_SS Not Asserted

tSPITDS

Sequential Transfer Delay

tSPICLKEXT – 1.5

tSDSCI

SPIx_SS Assertion to First SPIx_CLK Edge

11.7

tSSPID

Data Input Valid to SPIx_CLK Edge (Data Input Setup)

tHSPID

SPIx_CLK Sampling Edge to Data Input Invalid

1.6

Switching Characteristics

tDSOE

SPIx_SS Assertion to Data Out Active

14.12

tDSDHI

SPIx_SS Deassertion to Data High Impedance

12.6

tDDSPID

SPIx_CLK Edge to Data Out Valid (Data Out Delay)

14.16

tHDSPID

SPIx_CLK Edge to Data Out Invalid (Data Out Hold)

1.5

SPICLKEXT

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