ADSP-SC591 datasheet(9/145 Pages) AD

9 / 145 page

Rev. A

Page 9 of 145

April 2022

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

SIMD mode allows the processors to execute the same instruc-

tion in both processing elements, but each processing element

operates on different data. This architecture efficiently executes

math intensive DSP algorithms. In addition to all the features of

previous generation SHARC cores, the SHARC+ core also pro-

vides a new and simpler way to execute an instruction only on

the PEy data register.

SIMD mode doubles the bandwidth between memory and the

processing elements, as required for sustained computational

operation of two processing elements. When using the data

address generators (DAGs) to transfer data in SIMD mode, two

data values transfer with each memory or register file access.

Independent Parallel Computation Units

Within each processing element is a set of pipelined computa-

tional units. The computational units consist of a multiplier, an

ALU, and a shifter. These units are arranged in parallel, maxi-

mizing computational throughput. These computational units

support IEEE 32-bit single-precision floating-point; 40-bit

extended-precision floating-point; IEEE 64-bit double-preci-

sion floating-point; and 32-bit fixed-point data formats.

A multifunction instruction set supports parallel execution of

the ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments per core.

All processing operations take one cycle to complete. For all

floating-point operations, the processor takes two cycles to

complete in case of data dependency. Double-precision float-

ing-point data take two to six cycles to complete. The processor

stalls for the appropriate number of cycles for an interlocked

pipeline plus data dependency check.

Core Timer

Each SHARC+ processor core includes an extra timer. This

extra timer is clocked by the internal processor clock and is typ-

ically used as a system tick clock for generating periodic

operating system interrupts.

Data Register File

Each processing element contains a general-purpose data regis-

ter file. The register files transfer data between the computation

units and the data buses, and store intermediate results. These

10-port, 32-register register files (16 primary, 16 secondary),

combined with the enhanced Harvard architecture of the pro-

cessor, allow unconstrained data flow between computation

units and internal memory. The registers in the PEx data regis-

ter file are referred to as R0–R15 and in the PEy data register file

as S0–S15.

Context Switch

Many of the registers of the processor have secondary registers

that can activate during interrupt servicing for a fast context

switch. The data, DAG, and multiplier result registers have sec-

ondary registers. The primary registers are active at reset,

whereas control bits in MODE1 activate the secondary registers.

Universal Registers

General-purpose tasks use the universal registers. The four uni-

versal status (USTAT) registers allow easy bit manipulations

(set, clear, toggle, test, XOR) for all control and status peripheral

registers.

The data bus exchange register (PX) permits data to pass

between the 64-bit PM data bus and the 64-bit DM data bus or

between the 40-bit register file and the PM or DM data bus.

These registers contain hardware to handle the data width

difference.

Data Address Generators (DAG) With Zero Overhead

Hardware Circular Buffer Support

For indirect addressing and implementing circular data buffers

in hardware, the ADSP-2159x/ADSP-SC59x processors use two

data address generators (DAGs). Circular buffers allow efficient

programming of delay lines and other data structures required

in digital signal processing and are commonly used in digital fil-

ters and fast Fourier transforms (FFT). The DAGs contain

sufficient registers to allow the creation of up to 32 circular buf-

fers (16 primary register sets and 16 secondary sets). The DAGs

automatically handle address pointer wraparound, reduce over-

head, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

Flexible Instruction Set Architecture (ISA)

The flexible instruction set architecture (ISA), a 48-bit instruc-

tion word, accommodates various parallel operations for

concise programming. For example, the processors can condi-

tionally execute a multiply, an add, and a subtract in both

processing elements while branching and fetching up to four

32-bit values from memory—all in a single instruction. Addi-

tionally, the double-precision floating-point instruction set is

new to the SHARC+ core, as compared with the previous

SHARC core.

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from

previous SHARC core processors, the SHARC+ core processors

support 16-bit and 32-bit opcodes for many instructions, for-

merly 48-bit in the ISA. This variable instruction set

architecture (VISA) feature drops redundant or unused bits

within the 48-bit instruction to create more efficient and com-

pact code. The program sequencer supports fetching these

16-bit and 32-bit instructions from both internal and external

memories. VISA is not an operating mode; rather, it is address

dependent (refer to the ISA/VISA address spaces in Table 5).

Finally, the processor allows jumps between ISA and VISA

instruction fetches.

Single-Cycle Fetch of Instructional Four Operands

The ADSP-2159x/ADSP-SC59x processors feature an enhanced

Harvard architecture in which the DM bus transfers data and

the PM bus transfers both instructions and data.

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