ADSP-SC591 datasheet(8/145 Pages) AD

8 / 145 page

Rev. A

Page 8 of 145

April 2022

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

The system configuration is flexible, but a typical configuration

is 512 kb DM, 128 kb PM, and 128 kb of instruction cache, with

the remaining L1 memory configured as SRAM. Each address-

able memory space outside the L1 memory can be accessed

either directly or via cache.

The memory map in Table 2 gives the L1 memory address space

and shows multiple L1 memory blocks offering a configurable

mix of SRAM and cache.

L1 Requester and Completer Ports

Each SHARC+ core has two requester/completer ports to and

from the system fabric. One requester port fetches instructions.

The second requester port drives data to the system world.

Completer Port 1 together with Completer Port 2 memory

direct memory access (high speed MDMA and accelerators) run

conflict free access to the individual memory blocks. For the

completer port address, refer to the L1 memory address map in

Table 2.

L1 On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks, assuming no

block conflicts. The total bandwidth is realized using both the

DMD and PMD buses (2 × 64-bits CCLK speed and 2 × 32-bit

SYSCLK speed).

Instruction and Data Cache

The ADSP-2159x/ADSP-SC59x processors also include a

traditional instruction cache (I-cache) and two data caches

(D-caches, one each for PM/DM) with parity support for all

caches. These caches support one instruction access and two

data accesses over the DM and PM buses per CCLK cycle. The

cache controllers automatically manage the configured L1

memory. The system can configure part of the L1 memory for

automatic management by the cache controllers. The sizes of

these caches are independently configurable from 0 to 128 kB

each. The memory not managed by the cache controllers is

directly addressable by the processors. The controllers ensure

the data coherence between the two data caches. The caches

provide user controllable features such as full and partial lock-

ing, range bound invalidation, and flushing.

Core Memory-Mapped Registers (CMMR)

The core memory-mapped registers (CMMR) control the

L1 instruction and data cache, branch target buffer (BTB),

L2 cache, parity error, system control, debug, and monitor

functions.

SHARC+ CORE ARCHITECTURE

The ADSP-2159x/ADSP-SC59x processors are assembly code

compatible with all previous SHARC processors featuring the

SHARC or SHARC+ core, beginning with the first generation

ADSP-2106x SHARC processors and including the ADSP-

2116x, ADSP-2126x, ADSP-213xx, ADSP-214xx, and ADSP-

SC5xx/ADSP-215xx processors.

The SIMD architecture featured on the ADSP-2159x/ADSP-

SC59x processors is identical to all previous SIMD SHARC pro-

cessors, namely the ADSP-2116x, ADSP-2126x, ADSP-213xx,

ADSP-214xx, and ADSP-SC5xx/ADSP-215xx processors, as

shown in Figure 4 and as described in the following sections.

Single-Instruction, Multiple Data (SIMD) Computational

Engine

The SHARC+ core contains two computational processing ele-

ments that operate as a single-instruction, multiple data (SIMD)

engine.

The processing elements are referred to as PEx and PEy, each

containing an arithmetic logic unit (ALU), multiplier, shifter,

and register file. PEx is always active, and PEy is enabled by set-

ting the PEYEN mode bit in the mode control register

(MODE1).

Figure 5. ADSP-2159x/ADSP-SC59x Memory Map

RESERVED

0x FFFF FFFF

0x C000 0000

0x 8000 0000

0x 6000 0000

0x 5000 0000

0x 4C00 0000

0x 4800 0000

0x 4400 0000

0x 4000 0000

0x 3000 0000

0x 2840 0000

0x 2824 0000

0x 2023 0000

0x 2020 0000

DMC0 (1GB)

SPI2/OSPI0 FLASH ADDRESS SPACE (512MB)

SYSTEM MMR

SHARC2 L1 ADDRESS SPACE VIA

COMPLETER PORT 1/COMPLETER PORT 2

SHARC1 L1 ADDRESS SPACE VIA

COMPLETER PORT 1/COMPLETER PORT 2

RESERVED

L2 SRAM (16Mb)

RESERVED

L2 BOOT ROM 1 (0.5Mb)

L2 BOOT ROM 0 (0.5Mb)

(ARM BOOT ALIAS ADDRESS SPACE)

L2 BOOT ROM 2 (0.5Mb)

0x 2022 0000

0x 2021 0000

0x 2000 0000

0x 0039 FFFF

0x 0038 0000

0x 0031 FFFF

0x 0030 0000

0x 002E FFFF

0x 002C 0000

0x 0026 FFFF

0x 0024 0000

0x 0000 0000

RESERVED

L1 BLOCK 3 SRAM (1Mb)

RESERVED

L1 BLOCK 2 SRAM (1Mb)

L1 BLOCK 1 SRAM (1.5Mb)

L1 BLOCK 0 SRAM (1.5Mb)

RESERVED/CORE MMRs/

OTHER MEMORY ALIASES

RESERVED

ARM L2 CONFIG REGS (4KB)

RESERVED

ARM BOOT (64KB)

0x 2000 0000

0x 1000 1000

0x 1000 0000

0x 0000 FFFF

0x 0000 0000

0x 28BA 0000

0x 28A4 0000

**FOR THE ADSP-21591,THE 1MB (8Mb) L2 SRAM RANGE IS 0x20100000–0x201FFFFF.

ADSP-SC591 Datasheet(PDF) 8 Page - Analog Devices

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