ZSSC3123AI2R datasheet(32/62 Pages) RENESAS

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ZSSC3123 Datasheet

Nov 19, 2021

Page 32

Figure 17 for the I2C timing diagram, and see Table 21 for the definitions of the parameters shown in the diagram.

Figure 17. I2C Timing Diagram

Table 21. I2C Parameters

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

SCL clock frequency[a]

fSCL

400

kHz

Start condition hold time relative to SCL edge

tHDSTA

0.1

µs

Minimum SCL clock low width[b]

tLOW

0.6

µs

Minimum SCL clock high width[b]

tHIGH

0.6

µs

Start condition setup time relative to SCL edge

tSUSTA

0.1

µs

Data hold time on SDA relative to SCL edge

tHDDAT

0.5

µs

Data setup time on SDA relative to SCL edge

tSUDAT

0.1

µs

Stop condition setup time on SCL

tSUSTO

0.1

µs

Bus free time between stop condition and start condition

tBUS

µs

[a]The min. frequency of 20kHz applies to calibration/test only (required to meet Command Window timing). There is no minimum for NOM.

[b]Combined low and high widths must equal or exceed the minimum SCL period.

10.6.2 SPI Features and Timing

SPI is available only as half duplex (read-only from the ZSSC3123). SPI speeds of up to 800kHz can be supported. The SPI interface can be

programmed to allow the master to sample MISO on the falling-edge or rising-edge of SCL via the SPI_Phase bit in EEPROM word Cust_Config

(see Table 32 for bit assignments). See the following figure for the SPI timing diagram and the following table for definitions of the parameters

shown in the timing diagram.

SDA

SCL

tHDSTA

tHDDAT

tLOW

tSUDAT

tHIGH

tSUSTA

tHDSTA

tSUSTO

tBUS

ZSSC3123AI2R Datasheet(PDF) 32 Page - Renesas Technology Corp

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