ZSSC3123AI2R datasheet(33/62 Pages) RENESAS

33 / 62 page

ZSSC3123 Datasheet

Nov 19, 2021

Page 33

Figure 18. SPI Timing Diagram

Table 22. SPI Parameters

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

SCLK clock frequency

fSCL

800

kHz

SS drop to first clock edge

tHDSS

2.5

µs

Minimum SCLK clock low width[a]

tLOW

0.6

µs

Minimum SCLK clock high width[a]

tHIGH

0.6

µs

Clock edge to data transition

tCLKD

0.5

µs

Rise of SS relative to last clock edge

tSUSS

0.1

µs

Bus free time between rise and fall of SS

tBUS

µs

[a]Combined low and high widths must equal or exceed minimum SCLK period.

10.6.3 I2C and SPI Commands

As detailed in Table 23, there are three types of commands that allow the user to interface with the ZSSC3123 in the I2C or SPI modes.

Table 23. I2C and SPI Command Types

Type

Description

Communication Supported

Reference Sections

Data Fetch (DF)

Used to fetch data in any digital mode

I2C and SPI

Section 10.6.4

Measurement Request (MR)

Used to start measurements in Sleep Mode

I2C and SPI

Section 10.6.5

Calibration Commands

Used in Command Mode during the calibration process

I2C Only

Section 11.2

10.6.4 Data Fetch (DF)

The Data Fetch (DF) command is used to fetch data in any digital output mode. With the start of communication (for I2C after reading the slave

address; for SPI at the falling edge of SS), the entire output packet will be loaded in a serial output register. The register will be updated after

the communication is finished. The output is always scaled to 14 bits independent of the programmed resolution. The ordering of the bits is big-

endian.

tBUS

tLOW

SCLK

MISO

HiZ

tHDSS

tHIGH

tCLKD

tSUSS

HiZ

tCLKD

ZSSC3123AI2R Datasheet(PDF) 33 Page - Renesas Technology Corp

ZSSC3123AI2R Datasheet(HTML) 33 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL