ZSSC3123AI2R datasheet(21/62 Pages) RENESAS

21 / 62 page

ZSSC3123 Datasheet

Nov 19, 2021

Page 21

Symbol

Description

Temperature measurement capacitor

CTOFF

Temperature CDC zero shift

CTREF

Temperature reference capacitance

Temp_Trim

Temperature trim setting (bit setting in Table 31)

CDC_Offset

CDC offset trim setting (bit setting in Table 31)

CDC_Reference

CDC reference setting (bit setting in Table 31)

Note: The factory settings for Temp_Trim, CDC_Offset, and CDC_Reference are optimized for the full temperature range of -40°C to 125°C

guaranteeing a minimum effective resolution of 13 bits when 14 bits of resolution is selected. Unless a different temperature range is needed,

it is strongly recommended that these settings not be changed.

9.3

Digital Core

The digital core provides control logic for the analog front-end, performs input signal conditioning, and handles external communication. A digital

signal processor (DSP) is used for conditioning and correcting the converted sensor and temperature inputs. The DSP can correct for up to a

two-region piece-wise non-linear sensor input, and up to a second-order non-linear temperature input. Alternatively a third-order correction of

the sensor input for one region and up to a second-order, non-linear temperature input can be selected. Refer to section 13 for details on the

signal conditioning and correction math. The analog front-end configuration and correction coefficients for both the capacitive sensor and the

temperature sensor are stored in an on-chip EEPROM.

Four different types of outputs are available: I2C, SPI, PDM, and the Alarms. These output modes are used in combination with the two

measurement modes: Update Mode and Sleep Mode. For a full description of normal operation in each mode, refer to section 10.

The ZSSC3123 has an internal 1.85MHz temperature-compensated oscillator that provides the time base for all operations. When VDD exceeds

the POR level, the reset signal de-asserts and the clock generator starts. See section 10.1 for the subsequent power-on sequence. The exact

clock frequency influences the measurement cycle time (see the frequency variation spec in section 5). To minimize the oscillator error as the

VDD voltage changes, an on-chip regulator supplies the oscillator block.

ZSSC3123AI2R Datasheet(PDF) 21 Page - Renesas Technology Corp