DA14531 datasheet(66/374 Pages) DIALOG

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DA14531

Ultra Low Power Bluetooth 5.1 SoC

Final

Datasheet

Revision 3.1

09-Jul-2020

CFR0011-120-00

66 of 374

Table 38: Booting Sequence Steps

Step 1:

Boot from

external

SPI Master

Step 2: Boot

from 1-wire

UART (first

option)

Step 3:

Boot from

1-wire

UART

(second

option)

Step 4:

Boot from

2-wire

UART

Step 5:

Boot from

external

SPI Slave

Step 6:

Boot from

I2C

P0_0/RST

MISO

MOSI

P0_1

MOSI

SCS

P0_2

P0_3

SCS

RxTx

MISO

SDA

P0_4

SCK

SCL

P0_5

RxTx (Default)

P0_6

P0_7

P0_8

P0_9

P0_10

P0_11

If no bootable devices are found on any of the serial interfaces, the Booter can do two things,

depending on what is stored in the CS. If the "Debugger disable" (0x70000000) command is stored

there, the Booter will start scanning for peripherals again. Otherwise it enters the endless loop with

the debugger (JTAG) being enabled. The debugger can be connected to P0_5 in the WLCSP17

package or P0_10 in the FCGQFN24 package.

After the BootROM sequence has completed, the default system clock is RC32M, regardless of

which boot path has been chosen and all GPIOs are set back to their default reset values.

DA14531 Datasheet(PDF) 66 Page - Dialog Semiconductor

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