DA14531 datasheet(13/374 Pages) DIALOG

13 / 374 page

DA14531

Ultra Low Power Bluetooth 5.1 SoC

Final

Datasheet

Revision 3.1

09-Jul-2020

CFR0011-120-00

13 of 374

Table 136: XTAL32M_START_REG (0x50000030) ......................................................................... 202

Table 137: XTALRDY_CTRL_REG (0x50000034) ........................................................................... 202

Table 138: XTAL32M_CTRL0_REG (0x50000038) .......................................................................... 203

Table 139: POR_PIN_REG (0x50000040)........................................................................................ 203

Table 140: POR_TIMER_REG (0x50000042) .................................................................................. 203

Table 141: PMU_SLEEP_REG (0x50000050).................................................................................. 204

Table 142: POWER_CTRL_REG (0x50000052) .............................................................................. 204

Table 143: POWER_LEVEL_REG (0x50000054) ............................................................................ 205

Table 144: XTAL32M_TRSTAT_REG (0x50000032) ....................................................................... 205

Table 145: Register map crg2632_preg_tim_00 ............................................................................... 206

Table 146: CLK_RTCDIV_REG (0x5000424C) ................................................................................ 206

Table 147: Register map crg2632_dcdc_dig_00 .............................................................................. 207

Table 148: DCDC_CTRL_REG (0x50000080).................................................................................. 207

Table 149: Register map DMA .......................................................................................................... 209

Table 150: DMA0_A_STARTL_REG (0x50003600) ......................................................................... 210

Table 151: DMA0_A_STARTH_REG (0x50003602) ........................................................................ 210

Table 152: DMA0_B_STARTL_REG (0x50003604) ......................................................................... 210

Table 153: DMA0_B_STARTH_REG (0x50003606) ........................................................................ 210

Table 154: DMA0_INT_REG (0x50003608)...................................................................................... 211

Table 155: DMA0_LEN_REG (0x5000360A) .................................................................................... 211

Table 156: DMA0_CTRL_REG (0x5000360C) ................................................................................. 211

Table 157: DMA0_IDX_REG (0x5000360E) ..................................................................................... 213

Table 158: DMA1_A_STARTL_REG (0x50003610) ......................................................................... 213

Table 159: DMA1_A_STARTH_REG (0x50003612) ........................................................................ 213

Table 160: DMA1_B_STARTL_REG (0x50003614) ......................................................................... 213

Table 161: DMA1_B_STARTH_REG (0x50003616) ........................................................................ 213

Table 162: DMA1_INT_REG (0x50003618)...................................................................................... 213

Table 163: DMA1_LEN_REG (0x5000361A) .................................................................................... 214

Table 164: DMA1_CTRL_REG (0x5000361C) ................................................................................. 214

Table 165: DMA1_IDX_REG (0x5000361E) ..................................................................................... 216

Table 166: DMA2_A_STARTL_REG (0x50003620) ......................................................................... 216

Table 167: DMA2_A_STARTH_REG (0x50003622) ........................................................................ 216

Table 168: DMA2_B_STARTL_REG (0x50003624) ......................................................................... 216

Table 169: DMA2_B_STARTH_REG (0x50003626) ........................................................................ 216

Table 170: DMA2_INT_REG (0x50003628)...................................................................................... 216

Table 171: DMA2_LEN_REG (0x5000362A) .................................................................................... 217

Table 172: DMA2_CTRL_REG (0x5000362C) ................................................................................. 217

Table 173: DMA2_IDX_REG (0x5000362E) ..................................................................................... 218

Table 174: DMA3_A_STARTL_REG (0x50003630) ......................................................................... 218

Table 175: DMA3_A_STARTH_REG (0x50003632) ........................................................................ 219

Table 176: DMA3_B_STARTL_REG (0x50003634) ......................................................................... 219

Table 177: DMA3_B_STARTH_REG (0x50003636) ........................................................................ 219

Table 178: DMA3_INT_REG (0x50003638)...................................................................................... 219

Table 179: DMA3_LEN_REG (0x5000363A) .................................................................................... 219

Table 180: DMA3_CTRL_REG (0x5000363C) ................................................................................. 219

Table 181: DMA3_IDX_REG (0x5000363E) ..................................................................................... 221

Table 182: DMA_REQ_MUX_REG (0x50003680) ........................................................................... 221

Table 183: DMA_INT_STATUS_REG (0x50003682) ....................................................................... 222

Table 184: DMA_CLEAR_INT_REG (0x50003684) ......................................................................... 223

Table 185: Register map GPADC ..................................................................................................... 224

Table 186: GP_ADC_CTRL_REG (0x50001500) ............................................................................. 224

Table 187: GP_ADC_CTRL2_REG (0x50001502) ........................................................................... 225

Table 188: GP_ADC_CTRL3_REG (0x50001504) ........................................................................... 226

Table 189: GP_ADC_OFFP_REG (0x50001508) ............................................................................. 226

Table 190: GP_ADC_OFFN_REG (0x5000150A) ............................................................................ 226

Table 191: GP_ADC_TRIM_REG (0x5000150C) ............................................................................. 227

Table 192: GP_ADC_CLEAR_INT_REG (0x5000150E) .................................................................. 227

Table 193: GP_ADC_RESULT_REG (0x50001510) ........................................................................ 227

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