DA14531 datasheet(87/374 Pages) DIALOG

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DA14531

Ultra Low Power Bluetooth 5.1 SoC

Final

Datasheet

Revision 3.1

09-Jul-2020

CFR0011-120-00

87 of 374

11 OTP Controller

11.1 Introduction

The OTP controller realizes all functions of the OTP macro cell in an automated and transparent way.

The controller facilitates all data transfers (reading and programming), comprises a DMA engine

which connects to the AHB bus as a master, and has the highest priority to copy code from OTP into

SysRAM in mirrored mode. The block diagram is presented in Figure 30.

Features

● Implements all timing constraints for any access to the physical OTP cell

● Automatic single Error Code Correction (ECC) - 6 bits (implemented in the OTP cell)

● 32-bit read in a single read access from the OTP cell

● Single word buffer for programming. No burst programming supported

● Empty words are 0xFFFFFFFF. Zeros are programmed per 32-bit word

● Embedded DMA engine for fast mirroring of the OTP contents into the SysRAM

● Embedded DMA supports reading in bursts of 4 × 32-bit words

● Transparent random address access to the OTP memory cells via the AHB slave memory

interface

● Hardwired handshaking with the PMU to realize the mirroring procedure

Copy

Req/Ack

OTP Memory

(32+6)bits x 8192

DMA

AHB Slave

Memory

AHB Slave

Registers

AHB Lite

FIFO

Controller

IF Ctrl

Slave

AHB Master

Figure 30: OTP Controller Block Diagram

11.2 Architecture

The OTP controller block includes the OTP macro cell and pure digital logic implementing the

controlling functions. The OTP memory communicates with the controller through a proprietary

interface.

The internal organization of the OTP cell is 32-bit data and 6-bit ECC for each of the 8192

addressable positions. The six bits of the ECC are only accessible within the OTP cell. The ECC is

generated by the OTP cell during the programming and is used again by the OTP cell in a

transparent way during reading.

The AHB master interface is controlled by a DMA engine with an internal FIFO of eight 32-bit words.

The DMA engine supports AHB reads and writes. The AHB address where memory access should

begin is programmed into the DMA engine at OTPC_AHBADR_REG[OTPC_AHBADR]. The number

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