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DA14531 Datasheet(PDF) 68 Page - Dialog Semiconductor |
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DA14531 Datasheet(HTML) 68 Page - Dialog Semiconductor |
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68 / 374 page  DA14531 Ultra Low Power Bluetooth 5.1 SoC Final Datasheet Revision 3.1 09-Jul-2020 CFR0011-120-00 68 of 374 © 2020 Dialog Semiconductor The HW reset can also be automatically activated when the system wakes up from the Extended or Deep Sleep mode by programming the bit PMU_CTRL_REG[RESET_ON_WAKEUP]. The POR and the HW reset basically run the cold start-up sequence and the BootROM code is executed. The SW reset is the logical OR of a signal from the Cortex CPU (triggered by writing SCB->AIRCR = 0x05FA0004) and the SYS_CTRL_REG[SW_RESET] bit. It is mainly used to reboot the system after the base address has been remapped. The block diagram of the reset block is depicted in Figure 21. Certain registers are reset by POR only, or by POR and the HW reset signal but not by the SW reset. These registers are listed in Table 39. Table 39: Reset Signals and Registers Reset by POR Only Reset by POR or HW Reset Reset by POR, HW Reset, or SW Reset BANDGAP_REG BLE_CNTL2_REG The rest of the Register File POR_PIN_REG CLK_AMBA_REG[OTP_ENABLE] POR_TIMER_REG CLK_FREQ_TRIM_REG HWR_CTRL_REG CLK_RADIO_REG RESET_STAT_REG[PORESET_STAT] CLK_CTRL_REG PAD_LATCH_REG PMU_CTRL_REG POWER_AON_CTARL_REG SYS_CTRL_REG GP_DATA_REG TRIM_CTRL_REG TEST_VDD_REG RAM_PWR_CTRL_REG RTC_CONTROL_REG CLK_RC32K_REG RTC_KEEP_RTC_REG CLK_XTAL32K_REG CLK_RC32M_REG CLK_RCX_REG XTALRDY_CTRL_REG XTAL32M_CTRL0_REG PMU_SLEEP_REG POWER_CTRL_REG POWER_LEVEL_REG DCDC_CTRL_REG RAM_LPMX_REG HIBERN_CTRL_REG CLK_RTCDIV_REG RTC_CONTROL_REG RTC_KEEP_RTC_REG OTPC_*_REG QDEC_*_REG All RF calibration registers |
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