LTC6820 datasheet(39/92 Pages) AD

39 / 92 page

LTC6811-1/LTC6811-2

Rev. C

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OPERATION

Each S pin PWM signal is sequenced at different intervals

to ensure that no two pins switch on or off at the same

time. The switching interval between channels is 62.5ms,

and 0.75 seconds is required for all twelve pins to switch

(12 • 62.5ms).

The default value of the PWM register is all 1s so that the

LTC6811 will maintain backwards compatibility with the

LTC6804. Upon entering sleep mode, the PWM register

will be initialized to its default value.

I2C/SPI MASTER ON LTC6811 USING GPIOS

The I/O ports GPIO3, GPIO4 and GPIO5 on LTC6811-1 and

LTC6811-2 can be used as an I2C or SPI master port to

communicate to an I2C or SPI slave. In the case of an I2C

master, GPIO4 and GPIO5 form the SDA and SCL ports of

the I2C interface respectively. In the case of a SPI master,

GPIO3, GPIO4 and GPIO5 become the CSBM, SDIOM

and SCKM ports of the SPI interface respectively. The

SPI master on LTC6811 supports SPI mode 3 (CHPA = 1,

CPOL = 1).

The GPIOs are open drain outputs, so an external pull-up

is required on these ports to operate as an I2C or SPI

master. It is also important to write the GPIO bits to 1 in

the Configuration Register Group so these ports are not

pulled low internally by the device.

COMM Register

LTC6811hasa6-byteCOMMregisterasshowninTable 18.

This register stores all data and control bits required for

I2C or SPI communication to a slave. The COMM register

contains three bytes of data Dn[7:0] to be transmitted to

or received from the slave device. ICOMn[3:0] specify

control actions before transmitting/receiving each data

byte. FCOMn[3:0] specify control actions after transmit-

ting/receiving each data byte.

If the bit ICOMn[3] in the COMM register is set to 1 the

part becomes a SPI master and if the bit is set to 0 the

part becomes an I2C master.

Table 19 describes the valid write codes for ICOMn[3:0]

and FCOMn[3:0] and their behavior when using the part

as an I2C master.

Table 19. Write Codes for ICOMn[3:0] and FCOMn[3:0] on I2C Master

CONTROL BITS

CODE

ACTION

DESCRIPTION

ICOMn[3:0]

0110

START

Generate a START signal on I2C port followed by data transmission

0001

STOP

Generate a STOP signal on I2C port

0000

BLANK

Proceed directly to data transmission on I2C port

0111

No Transmit

Release SDA and SCL and ignore the rest of the data

FCOMn[3:0]

0000

Master ACK

Master generates an ACK signal on ninth clock cycle

1000

Master NACK

Master generates a NACK signal on ninth clock cycle

1001

Master NACK + STOP

Master generates a NACK signal followed by STOP signal

LTC6820 Datasheet(PDF) 39 Page - Analog Devices

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