LTC6820 datasheet(21/92 Pages) AD

21 / 92 page

LTC6811-1/LTC6811-2

Rev. C

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OPERATION

EXTENDED BALANCING State

The watchdog timer has timed out, but the discharge

timer has not yet timed out (DTEN = 1). Discharge by

PWM may be in progress. If a WAKEUP signal is received,

the LTC6811 will transition from EXTENDED BALANCING

state to STANDBY state.

isoSPI STATE DESCRIPTIONS

Note: The LTC6811-1 has two isoSPI ports (A and B), for

daisy-chain communication. The LTC6811-2 has only one

isoSPI port (A), for parallel-addressable communication.

IDLE State

The isoSPI ports are powered down.

When isoSPI Port A receives a WAKEUP signal (see Wak-

ing Up the Serial Interface), the isoSPI enters the READY

state. This transition happens quickly (within tREADY) if

the Core is in the STANDBY state because the DRIVE and

VREG pins are already biased up. If the Core is in the SLEEP

state when the isoSPI receives a WAKEUP signal, the part

transitions to the READY state within tWAKE.

READY State

The isoSPI port(s) are ready for communication. Port B

is enabled only for LTC6811-1, and is not present on the

LTC6811-2.Theserialinterfacecurrentinthisstatedepends

on if the part is LTC6811-1 or LTC6811-2, the status of the

ISOMD pin and RBIAS = RB1 + RB2 (the external resistors

tied to the IBIAS pin).

If there is no activity (i.e. no WAKEUP signal) on Port

A for greater than tIDLE = 5.5ms, the LTC6811 goes to

the IDLE state. When the serial interface is transmitting

or receiving data the LTC6811 goes to the ACTIVE state.

ACTIVE State

TheLTC6811istransmitting/receivingdatausingoneorbothof

the isoSPI ports. The serial interface consumes maximum

power in this state. The supply current increases with

clock frequency as the density of isoSPI pulses increases.

POWER CONSUMPTION

The LTC6811 is powered via two pins: V+ and VREG. The

V+ input requires voltage greater than or equal to the

top cell voltage minus 0.3V, and it provides power to

the high voltage elements of the core circuitry. The VREG

input requires 5V and provides power to the remaining

core circuitry and the isoSPI circuitry. The VREG input can

be powered through an external transistor, driven by the

regulated DRIVE output pin. Alternatively, VREG can be

Thepowerconsumptionvariesaccordingtotheoperational

states.Table 1andTable 2provideequationstoapproximate

the supply pin currents in each state. The V+ pin current

depends only on the Core state. However, the VREG pin

current depends on both the Core state and isoSPI state,

and can therefore be divided into two components. The

isoSPI interface draws current only from the VREG pin.

IREG = IREG(Core) + IREG(isoSPI)

Table 1. Core Supply Current

STATE

IVP

IREG(CORE)

SLEEP

VREG = 0V

4.1µA

0µA

VREG = 5V

1.9µA

2.2µA

STANDBY

13µA

40µA

REFUP

550µA

450µA

MEASURE

550µA

11.5mA

In the SLEEP state the VREG pin will draw approximately

2.2µA if powered by an external supply. Otherwise, the V+

pin will supply the necessary current.

LTC6820 Datasheet(PDF) 21 Page - Analog Devices

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