LTC6820 datasheet(69/92 Pages) AD

69 / 92 page

LTC6811-1/LTC6811-2

Rev. C

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voltage for the V+ pin. The circuit still uses the DRIVE

pin to generate VREG. This circuit minimizes the system

imbalance from the LTC6811 since the supply current

will only be drawn from the batteries during shutdown. It

is critical to add a diode between the top monitored cell

and V+ so that supply current will not conduct through

parasitic paths inside the IC during shutdown.

INTERNAL PROTECTION AND FILTERING

Internal Protection Features

The LTC6811 incorporates various ESD safeguards to

ensure robust performance. An equivalent circuit showing

the specific protection structures is shown in Figure 37.

While pins 43 to 48 have different functionality for the

–1 and –2 variants, the protection structure is the same.

Zener-likesuppressorsareshownwiththeirnominalclamp

voltage, while the unmarked diodes exhibit standard PN

junction behavior.

Filtering of Cell and GPIO Inputs

The LTC6811 uses a delta-sigma ADC, which includes a

delta-sigma modulator followed by a SINC3 finite impulse

response (FIR) digital filter. This greatly relaxes input

filtering requirements. Furthermore, the programmable

oversampling ratio allows the user to determine the best

trade-off between measurement speed and filter cutoff

frequency. Even with this high order low pass filter, fast

transientnoisecanstillinducesomeresidualnoiseinmea-

surements,especiallyinthefasterconversionmodes.This

can be minimized by adding an RC low pass decoupling to

eachADCinput,whichalsohelpsrejectpotentiallydamag-

ing high energy transients. Adding more than about 100Ω

to the ADC inputs begins to introduce a systematic error

in the measurement, which can be improved by raising

the filter capacitance or mathematically compensating in

software with a calibration procedure. For situations that

demand the highest level of battery voltage ripple rejec-

tion, grounded capacitor filtering is recommended. This

configuration has a series resistance and capacitors that

decouple HF noise to V–. In systems where noise is less

APPLICATIONS INFORMATION

C12

S12

C11

S11

C10

S10

V–

IPB

IMB

ICMP

IBIAS

SDO (NC)

SDI (NC)

SCK (IPA)

CSB (IMA)

ISOMD

WDT

DRIVE

VREG

DTEN

VREF1

VREF2

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

68111 F37

V+

LTC6811

96V

24V

12V

NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 35

Figure 37. Internal ESD Protection Structures of the LTC6811

LTC6820 Datasheet(PDF) 69 Page - Analog Devices

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