LTC6820 datasheet(42/92 Pages) AD

42 / 92 page

LTC6811-1/LTC6811-2

Rev. C

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OPERATION

Timing Specifications of I2C and SPI Master

The timing of the LTC6811 I2C or SPI master will be

controlled by the timing of the communication at the

LTC6811’s primary SPI interface. Table 22 shows the

I2C master timing relationship to the primary SPI clock.

Table 23 shows the SPI master timing specifications.

Table 22. I2C Master Timing

I2C MASTER

PARAMETER

TIMING RELATIONSHIP

TO PRIMARY SPI

INTERFACE

TIMING

SPECIFICATIONS

AT tCLK = 1µs

SCL Clock Frequency

1/(2 • tCLK)

Max 500kHz

tHD;STA

Min 200ns

tLOW

tCLK

Min 1µs

tHIGH

tCLK

Min 1µs

tSU;STA

tCLK + t4*

Min 1.03µs

tHD;DAT

t4*

Min 30ns

tSU;DAT

Min 200ns

tSU;STO

tCLK + t4*

Min 1.03µs

tBUF

3 • tCLK

Min 3µs

* Note: When using isoSPI, t4 is generated internally and is a minimum of

30ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high

times of the SCK input, each with a specified minimum of 200ns.

SDIOM (GPIO4)

68111 F14

SCKM (GPIO5)

CSBM HIGH/NO TRANSMIT

CSBM (GPIO3)

SDIOM (GPIO4)

SCKM (GPIO5)

CSBM (GPIO3)

CSBM LOW

CSBM LOW ≥ HIGH

SDIOM (GPIO4)

SCKM (GPIO5)

CSBM (GPIO3)

CSBM HIGH ≥ LOW

CSBM LOW

(SCK)

tCLK

Figure 14. STCOMM Timing Diagram for a SPI Master

Table 23. SPI Master Timing

SPI MASTER

PARAMETER

TIMING RELATIONSHIP

TO PRIMARY SPI

INTERFACE

TIMING

SPECIFICATIONS

AT tCLK = 1µs

SDIOM Valid to SCKM Rising

Setup

Min 200ns

SDIOM Valid from SCKM

Rising Hold

tCLK + t4*

Min 1.03µs

SCKM Low

tCLK

Min 1µs

SCKM High

tCLK

Min 1µs

SCKM Period (SCKM_Low +

SCKM_High)

2 • tCLK

Min 2µs

CSBM Pulse Width

3 • tCLK

Min 3µs

SCKM Rising to CSBM

Rising

5 • tCLK + t4*

Min 5.03µs

CSBM Falling to SCKM

Falling

Min 200ns

CSBM Falling to SCKM

Rising

tCLK + t3

Min 1.2µs

SCKM Falling to SDIOM Valid

Master requires < tCLK

* Note: When using isoSPI, t4 is generated internally and is a minimum of

30ns. Also, t3 = tCLK – t4. When using SPI, t3 and t4 are the low and high

times of the SCK input, each with a specified minimum of 200ns.

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