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CS43131 Datasheet(PDF) 114 Page - Cirrus Logic

Part # CS43131
Description  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection
PDF  156 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43131 Datasheet(HTML) 114 Page - Cirrus Logic

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114
DS1155F1
CS43131
7.1 Global Registers
7.1.6
System Clocking Control
Address 0x10006
R/W
76543210
—
MCLK_INT
MCLK_SRC_SEL
Default
00000110
Bits
Name
Description
7:3
—
Reserved
2
MCLK_INT
The frequency of internal MCLK.
0 Internal MCLK is expected to be 24.576 MHz
1 (Default) Internal MCLK is expected to be 22.5792 MHz
1:0
MCLK_SRC_
SEL
Select the source of internal MCLK.
00 Direct MCLK/XTAL Mode
01 PLL Mode
10 (Default) RCO Mode
11 Reserved
7.1.7
Serial Port Sample Rate
Address 0x1000B
R/W
76543210
—
ASP_SPRATE
Default
00000001
Bits
Name
Description
7:4
—
Reserved
3:0 ASP_SPRATE ASP sample rate. This register must be programmed for both Master Mode and Slave Mode operation. If ASP_SPRATE
= 384 kHz and the CS43131 operates in Master Mode, MCLK_INT is required to be 24.576 MHz. For all other rates,
MCLK_INT can be either 22.5792 MHz or 24.576 MHz.
0000 32 kHz
0001 (Default) 44.1 kHz
0010 48 kHz
0011 88.2 kHz
0100 96 kHz
0101 176.4 kHz
0110 192 kHz
0111 352.8 kHz
1000 384 kHz
1001–1111 Reserved
7.1.8
Serial Port Sample Bit Size
Address 0x1000C
R/W
76543210
—
XSP_SPSIZE
ASP_SPSIZE
Default
00000101
Bits
Name
Description
7:4
—
Reserved
3:2 XSP_SPSIZE XSP sample bit size.
00 32 bits
01 (Default) 24 bits
10–11 Reserved
1:0 ASP_SPSIZE ASP sample bit size.
00 32 bits
01 (Default) 24 bits
10 16 bits
11 8 bits
7.1.9
Pad Interface Configuration
Address 0x1000D
R/W
76543210
—
XSP_3ST
ASP_3ST
Default
00000011
Bits
Name
Description
7:2
—
Reserved



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