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CS43131 Datasheet(PDF) 118 Page - Cirrus Logic |
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CS43131 Datasheet(HTML) 118 Page - Cirrus Logic |
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118 / 156 page ![]() 118 DS1155F1 CS43131 7.3 ASP and XSP Registers 7.3 ASP and XSP Registers 7.3.1 CLKOUT Control Address 0x40004 R/W 76543210 — CLKOUT_DIV CLKOUT_SEL Default 00000000 Bits Name Description 7:5 — Reserved 4:2 CLKOUT_DIV Divider setting on internal MCLK path to CLKOUT. 000 (Default) Divide by 2 001 Divide by 3 010 Divide by 4 011 Divide by 8 100–111 Reserved 1:0 CLKOUT_SEL Select the source of CLKOUT. 00 (Default) XTAL/MCLK path 01 PLL output path 10–11 Reserved 7.3.2 ASP Numerator 1 Address 0x40010 R/W 76543210 ASP_N_LSB Default 00000001 Bits Name Description 7:0 ASP_N_LSB The value in this register cannot be changed while the serial port is powered up. ASP sample rate fractional divide numerator LSB. Along with ASP_M_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) ASP_N = 1 7.3.3 ASP Numerator 2 Address 0x40011 R/W 76543210 ASP_N_MSB Default 00000000 Bits Name Description 7:0 ASP_N_MSB The value in this register cannot be changed while the serial port is powered up. ASP sample rate fractional divide numerator MSB. Along with ASP_M_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) ASP_N = 1 7.3.4 ASP Denominator 1 Address 0x40012 R/W 76543210 ASP_M_LSB Default 00001000 Bits Name Description 7:0 ASP_M_LSB The value in this register cannot be changed while the serial port is powered up. ASP sample rate fractional divide denominator LSB. Along with ASP_N_MSB/LSB, selects the fractional divide value for setting the SCLK frequency. (Default) ASP_M = 8 |
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