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CS43131 Datasheet(PDF) 120 Page - Cirrus Logic

Part # CS43131
Description  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection
PDF  156 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43131 Datasheet(HTML) 120 Page - Cirrus Logic

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DS1155F1
CS43131
7.3 ASP and XSP Registers
7.3.10 ASP Clock Configuration
Address 0x40018
R/W
76543210
—ASP_M/SB
ASP_SCPOL_
OUT
ASP_SCPOL_
IN
ASP_LCPOL_
OUT
ASP_LCPOL_
IN
Default
00001100
Bits
Name
Description
7:5
—
Reserved
4
ASP_M/SB
ASP port master or slave configuration.
0 (Default) Slave Mode (input)
1 Master Mode (output)
3ASP_SCPOL_
OUT
ASP SCLK output drive polarity.
0Normal
1 (Default) Inverted
2ASP_SCPOL_
IN
ASP SCLK input polarity (pad to logic).
0Normal
1 (Default) Inverted
1
ASP_LCPOL_
OUT
ASP LRCK output drive polarity.
0 (Default) Normal
1Inverted
0
ASP_LCPOL_
IN
ASP LRCK input polarity (pad to logic).
0 (Default) Normal
1Inverted
7.3.11 ASP Frame Configuration
Address 0x40019
R/W
76543210
—
ASP_STP
ASP_5050
ASP_FSD
Default
00001010
Bits
Name
Description
7:5
—
Reserved
4
ASP_STP
ASP start phase. Controls which LRCK/FSYNC phase starts a frame.
0 (Default) The frame begins when LRCK/FSYNC transitions from high to low
1 The frame begins when LRCK/FSYNC transitions from low to high
3
ASP_5050
ASP LRCK fixed 50/50 duty cycle.
0 Programmable duty cycle per ASP_LCHI and ASP_LCPR.
1 (Default) Fixed 50% duty cycle
2:0
ASP_FSD
ASP frame start delay (units of ASP_SCLK periods).
000 0 delay
001 0.5 delay
010 (Default) 1.0 delay
...
101 2.5 delay
110–111 Reserved
7.3.12 XSP Numerator 1
Address 0x40020
R/W
76543210
XSP_N_LSB
Default
00000001
Bits
Name
Description
7:0
XSP_N_LSB The value in this register cannot be changed while the serial port is powered up.
XSP sample rate fractional divide numerator LSB. Along with XSP_M_MSB/LSB, selects the fractional divide value for
setting the SCLK frequency.
(Default) XSP_N = 1



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