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CS43131 Datasheet(PDF) 122 Page - Cirrus Logic

Part # CS43131
Description  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection
PDF  156 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43131 Datasheet(HTML) 122 Page - Cirrus Logic

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122
DS1155F1
CS43131
7.3 ASP and XSP Registers
7.3.18 XSP LRCK Period 1
Address 0x40026
R/W
76543210
XSP_LCPR_LSB
Default
00111111
Bits
Name
Description
7:0
XSP_LCPR_
LSB
The value in this register cannot be changed while the serial port is powered up.
XSP LRCK period, in units of XSP_SCLK periods stored in XSP_LCPR_LSB/MSB.
(Default) XSP_LCPR = 63
7.3.19 XSP LRCK Period 2
Address 0x40027
R/W
76543210
XSP_LCPR_MSB
Default
00000000
Bits
Name
Description
7:0
XSP_LCPR_
MSB
The value in this register cannot be changed while the serial port is powered up.
XSP LRCK period, in units of XSP_SCLK periods stored in XSP_LCPR_LSB/MSB.
(Default) XSP_LCPR = 63
7.3.20 XSP Clock Configuration
Address 0x40028
R/W
76543210
—XSP_M/SB
XSP_SCPOL_
OUT
XSP_SCPOL_
IN
XSP_LCPOL_
OUT
XSP_LCPOL_
IN
Default
00001100
Bits
Name
Description
7:5
—
Reserved
4
XSP_M/SB
XSP port master or slave configuration.
0 (Default) Slave Mode (input)
1 Master Mode (output)
3XSP_SCPOL_
OUT
XSP SCLK output drive polarity.
0Normal
1 (Default) Inverted
2XSP_SCPOL_
IN
XSP SCLK input polarity (pad to logic).
0Normal
1 (Default) Inverted
1
XSP_LCPOL_
OUT
XSP LRCK output drive polarity.
0 (Default) Normal
1Inverted
0
XSP_LCPOL_
IN
XSP LRCK input polarity (pad to logic).
0 (Default) Normal
1Inverted
7.3.21 XSP Frame Configuration
Address 0x40029
R/W
76543210
—
XSP_STP
XSP_5050
XSP_FSD
Default
00001010
Bits
Name
Description
7:5
—
Reserved
4
XSP_STP
XSP start phase. Controls which LRCK/FSYNC phase starts a frame.
0 (Default) The frame begins when LRCK/FSYNC transitions from high to low
1 The frame begins when LRCK/FSYNC transitions from low to high
3
XSP_5050
XSP LRCK fixed 50/50 duty cycle.
0 Programmable duty cycle per XSP_LCHI and XSP_LCPR
1 (Default) Fixed 50% duty cycle



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