CS43131 datasheet(125/156 Pages) CIRRUS

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DS1155F1

125

CS43131

7.4 DSD Registers

7.4.2

DSD Volume A

Address 0x70001

R/W

76543210

DSD_VOLUME_A

Default

01111000

Bits

Name

Description

7:0

DSD_

VOLUME_A

Digital volume control registers for channel A. See DSD_VOLUME_B for description.

7.4.3

DSD Processor Path Signal Control 1

Address 0x70002

R/W

76543210

DSD_RAMP_

DSD_VOL_

BEQA

DSD_SZC

—

DSD_AMUTE DSD_AMUTE_

BEQA

DSD_MUTE_A DSD_MUTE_B

Default

10101000

Bits

Name

Description

DSD_RAMP_

Soft volume ramp-up after error. An unmute is performed after any error is recovered.

0 Immediate unmute is performed

1 (Default) Unmute behavior is controlled by DSD_SZC settings

6DSD_VOL_

BEQA

DSD_VOLUME_B equals DSD_VOLUME_A.

0 (Default) Volume setting of both channels in DSD processor are controlled independently

1 Volume setting of both channels are controlled by DSD_VOLUME_A. DSD_VOLUME_B is ignored

DSD_SZC

Soft ramp control.

0 Immediate change

1 (Default) Soft ramp

4—

Reserved

DSD_AMUTE DSD auto mute.

0 Function disabled

1 (Default) Mute occurs after reception of 256 repeated 8-bit DSD mute patterns. A single bit not fitting the repeated

pattern releases the mute. Detection and muting is done independently for each channel.

2DSD_

AMUTE_

BEQA

DSD Processor Auto mute channel B equals channel A.

0 (Default) Function disabled

1 Only mute when both channels AMUTE conditions are detected

1DSD_MUTE_

DSD Processor Channel A mute.

0 (Default) Function is disabled

1 Channel output is muted. Muting function is affected by the DSD_SZC bit

0DSD_MUTE_

DSD Processor Channel B mute.

0 (Default) Function is disabled.

1 Channel output is muted. Muting function is affected by the DSD_SZC bit.

7.4.4

DSD Interface Configuration

Address 0x70003

R/W

76543210

—

DSD_M/SB

DSD_PM_EN DSD_PM_SEL

Default

00000000

Bits

Name

Description

7:3

—

Reserved

DSD_M/SB

DSD clock master or Slave Mode.

0 (Default) Slave Mode

1 Master Mode

DSD_PM_EN DSD phase modulation mode. Can only be used when DSD_SPEED = 00 (64•Fs) or 01 (128•Fs).

0 (Default) this function is disabled (DSD normal mode)

1 DSD phase modulation input mode is enabled, and the DSD_PM_SEL bit must be set accordingly.

DSD_PM_SEL DSD phase modulation mode select.

0 (Default) The 2x data rate (BCKA) clock must be input to DSD_SCLK for phase modulation mode.

1 The 1x data rate (BCKD) clock must be input to DSD_SCLK for phase modulation mode.

CS43131 Datasheet(PDF) 125 Page - Cirrus Logic

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