CS43131 datasheet(127/156 Pages) CIRRUS

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DS1155F1

127

CS43131

7.5 Headphone and PCM Registers

DSD_HPF_EN Enable the high pass filter in the DSD processor.

0 HPF disabled

1 (Default) Enable HPF in the DSD processor

5—

Reserved

4SIGCTL_

DSDEQPCM

Enable DSD signal path control register bits to be controlled by PCM setting. DSD setting is ignored. Register bits

affected are the following:

DSD_RAMP_UP, DSD_VOL_BEQA, DSD_SZC, DSD_AMUTE, DSD_AMUTE_BEQA, DSD_MUTE_A, DSD_MUTE_B,

DSD_INV_A, DSD_INV_B, DSD_SWAP_CHAN, DSD_COPY_CHAN

After set, each DSD_x register bit is equal to setting of PCM_x register bit.

0 (Default) Function is disabled

1 Function is enabled

DSD_INV_A DSD Processor Channel A signal invert.

0 (Default) Function is disabled

1 Signal polarity of channel A is inverted

DSD_INV_B DSD Processor Channel B signal invert

0 (Default) the function is disabled

1 Signal polarity of channel B is inverted

DSD_SWAP_

CHAN

Swap channels A and B at the input. This bit takes effect before DSD_COPY_CHAN and DSD_INV_x.

0 (Default) Function disabled

1 Enable channel A and B swapping

0DSD_COPY_

CHAN

Copy channel A to channel B. This bit takes effect after DSD_SWAP_CHAN, but before DSD_INV_x.

0 (Default) Function disabled

1 Enable copy A to B function

7.5.1

HP Output Control 1

Address 0x80000

R/W

76543210

HP_CLAMPA

HP_CLAMPB

OUT_FS

HP_IN_EN

HP_IN_LP

—

+1dB_EN

Default

00110000

Bits

Name

Description

HP_CLAMPA Opt-out on clamping HPOUTA output to ground when PDN_HP is enabled.

0 (Default) Function disabled. HPOUTA is clamped when PDN_HP is set and HP_IN_EN is cleared. HPOUT is not

clamped when PDN_HP is cleared.

1 HPOUTA clamp is released if and only if PDN_HP is set.

HP_CLAMPB Opt-out on clamping HPOUTB output to ground when PDN_HP is enabled.

0 (Default) Function disabled. HPOUTB is clamped when PDN_HP is set and HP_IN_EN is cleared. HPOUT is not

clamped when PDN_HP is cleared.

1 HPOUTB clamp is released if and only if PDN_HP is set.

5:4

OUT_FS

Output full scale setting. This setting must only be updated when PDN_HP is set.

00 0.5 V

01 1 V

10 1.41 V

11 (Default) 1.73 V

HP_IN_EN

HPIN switches enable.

0 (Default) Switch open

1 Switch closed

HP_IN_LP

When selected, HPIN mode is placed into low power mode. This setting is only in effect when HP_IN_EN = 1. It should

only be set after HP_IN_EN = 1. It should be cleared before HP_IN_EN is cleared. When HP_IN_LP = 1, the maximum

supported speed for I2C is 400 kHz.

0 (Default) HPINx path is not in the power mode.

1 HPINx path is in the low power mode.

1—

Reserved

+1dB_EN

If selected, output full scale voltage is at 2 V. This setting is only in effect when OUT_FS = 11 and HV_EN = 1. This setting

is ignored if OUT_FS and HV_EN is set to any other settings. It should only be updated when PDN_HP is set.

0 (Default) Output full scale voltage is determined by OUT_FS setting.

1 Output full scale voltage is at 2 V.

Bits

Name

Description

CS43131 Datasheet(PDF) 127 Page - Cirrus Logic

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