Step 7.

Calculate the maximum power dissipation on external resistance and inside SRK1001:

Pd_Rext= Pd_AUX−PdCC*Rext

Rtot = 45.971mW−7.072mW*1.2kΩ

1.24kΩ

=37.64mW

Pd_SRK=Pd_AUX−Pd_Rext=45.971mW−37.64mW=8.33mW

The following figure shows VAUX pin operation during the various circuit phases (start-up phase, CC-CV

regulation and mains turn-off).

Figure 15. VAUX pin operation

VAUX

VCC_ON

VOUT

SO_COMP out

VCC_OFF

VCC_SO_ON

VCC

5.10

Operation in CC regulation and short circuit

During CC regulation operation in QR applications, the demagnetization time progressively increases while

reducing the load impedance and the output voltage consequently reduces. Therefore, the conduction duty cycle

of SR MOSFET driving progressively increases. The SRK1001 fixes a maximum driving pulse width level to

TON_MAX, and after this time interval has elapsed, it turns off the SR MOSFET. This means that, for the rest of the

demagnetization time after TON_MAX, the rectified current will continue flowing through the body diode.

If CC regulation is extended to short-circuit conditions (i.e., the output current is also regulated during short-circuit

and the primary controller does not enter hiccup protection), some care must be taken to avoid temperature

increase in the SR MOSFET, such as appropriate thermal design or the usage of an external schottky diode.

5.11

Adaptive gate drive

The IC is provided with a low-noise, high-current gate-drive output, capable of directly driving N-channel Power

MOSFETs.

The high-level voltage provided by the driver is in fact clamped at VGDclamp (11.6 V typ.) through accurate

circuitry. This avoids excessive voltage levels on the gate when the device is supplied with a high VCC, thus

minimizing the gate charge provided in each switching cycle.

Furthermore, the gate driver has a pull-down capability that ensures the SR MOSFET cannot be spuriously turned

on even at low VCC. In fact, the driver has a 1 V (typ.) saturation level at VCC below the turn-on threshold.

In order to optimize efficiency at low load levels (where driving losses may be relevant with respect to conduction

losses), the high-level of driver output is adapted, decreasing with decreasing demagnetization time. The adaptive

gate drive changes the driving high-level VHIGH in 16 steps of 400 mV, corresponding to 16 steps of detected

demagnetization time TD of the transformer, as described by the following relationships:

TD=300ns+TON_min*n+6

6

VHIGH=VGDclamp– 16–n*VGD_ad_step

where VGD_ad_step is the voltage step and n = 1 to 16 is the step number.

The voltage step increase or decrease is performed after the demagnetization time interval TD has been detected

longer or shorter by one step for 32 consecutive cycles..

SRK1001

Operation in CC regulation and short circuit

DS13155 - Rev 1

page 18/27