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MPC8540 Datasheet(PDF) 588 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 588 Page - Freescale Semiconductor, Inc |
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588 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 13-84 Freescale Semiconductor Local Bus Controller 13.5 Initialization/Application Information 13.5.1 Interfacing to Peripherals 13.5.1.1 Multiplexed Address/Data Bus and Unmultiplexed Address Signals To save pins on the local bus, address and data are multiplexed onto the same 32 bit bus. An external latch is needed to demultiplex and reconstruct the original address. No external intelligence is needed, because the LALE signal provides the correct timing to control a standard logic latch. The LAD pins can be directly connected to the data signals of the memory/peripheral. Transactions on the local bus start with an address phase, where the LBC drives the transaction address on the LAD signals and asserts the LALE signal. This can be used to latch the address and then the LBC can continue with the data phase. The LBC supports port sizes of 8,16, and 32 bit. For devices smaller than 32 bits, transactions must be broken down. For this reason, LA[30:31] are driven unmultiplexed. For 8-bit devices, LA[30:31] should be used and for 16-bit devices, LA[30] should be used. 32-bit devices use neither of these signals. In addition, the LBC supports burst transfers (not in the GPCM machine). LA[27:29] are the burst addresses within a natural 32-byte burst. To minimize the amount of address phases needed on the local bus and to optimize the throughput, those signals are driven separately and should be used whenever a device requires the 5 least significant addresses. Those should not be used from LAD[27:31]. All other addresses, A[0:26], must be reconstructed through the latch. Figure 13-68. Multiplexed Address/Data Bus 13.5.1.2 Peripheral Hierarchy on the Local Bus To achieve high bus speed interfaces for synchronous SRAMs or SDRAMs, a hierarchy of the memories/peripherals connected to the local bus is suggested, as shown in Figure 13-69. Muxed Address/Data Unmuxed Address LA[27:31] LAD[0:31] LALE Local Bus Interface Latch A[0:26] D Q LE A[27:31] D[0:31] |
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