MPC8540 datasheet(592/1302 Pages) FREESCALE

592 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-88

Freescale Semiconductor

Local Bus Controller

13.5.2.2

Read Data Phase After Address Phase

During the address phase, LAD actively drives the address and LBCTL is high, driving the bus

transceivers in the same direction as during a write. After the end of the address phase, LBCTL

goes low and changes the direction of the bus transceiver. The LBC places the LAD signals in high

impedance after its tdis(LB). The LBCTL will have its new state after ten(LB) and, because this is

an asynchronous input, the transceiver starts to drive those signals after its ten(transceiver) time.

The system designer has to ensure, that [ten(LB) + ten(transceiver)] is larger than tdis (LB) to avoid

bus contention.

13.5.2.3

Read-Modify-Write Cycle for Parity Protected Memory Banks

Principally, a read-modify-write cycle is a read cycle immediately followed by a write cycle.

Because the write cycle will have a new address phase in any case, this basically is the same case

as an address phase after a previous read.

13.5.2.4

UPM Cycles with Additional Address Phases

The flexibility of the UPM allows the user to insert additional address phases during read cycles

by changing the AMX field, therefore turning around the bus during one pattern. The LBC

automatically inserts a single bus turnaround cycle if the bus (LAD) was previously high

impedance for any reason, such as a read, before LALE is driven and LAD is driven with the new

address. The turnaround cycle is not inserted on a write, because the bus was already driven to

begin with.

However, bus contention could potentially still occur on the far side of a bus transceiver. It is the

responsibility of the designer of the UPM pattern to guarantee that enough idle cycles are inserted

in the UPM pattern to avoid this.

13.5.3 Interface to Different Port-Size Devices

The LBC supports 8-, 16-, and 32-bit data port sizes. However, the bus requires that the portion of

the data bus used for a transfer to or from a particular port size be fixed. A 32-bit port must reside

on D[0:31], a 16-bit port must reside on D[0:15], and an 8-bit port must reside on D[0:7]. The local

bus always tries to transfer the maximum amount of data on all bus cycles. Figure 13-73 shows

the device connections on the data bus.

MPC8540 Datasheet(PDF) 592 Page - Freescale Semiconductor, Inc