MPC8540 datasheet(589/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-85

Figure 13-69. Local Bus Peripheral Hierarchy

The multiplexed address/data bus sees the capacitive loading of the data pins of the fast SDRAMs

or synchronous SRAMs plus one load for an address latch plus one load for a buffer to the slow

memories. The loadings of all other memories and peripherals are hidden behind the buffer and

the latch. The system designer needs to investigate the loading scenario and ensure that I/O timings

can be met with the loading determined by the connected components.

13.5.1.3

Peripheral Hierarchy on the Local Bus for Very High Bus Speeds

To achieve the highest possible bus speeds on the local bus, it is recommended to reduce the

number of devices connected directly to the local bus even further. For those cases probably only

one bank of synchronous SRAMs or SDRAMs should be used and instead of using a separate latch

and a separate bus transceiver, a bus demultiplexer combining those two functions into one device

should be used. Figure 13-70 shows an example of such a hierarchy. This section is only a

guideline and the board designer must simulate the electric characteristics of his scenario to

determine the maximum operating frequency.

Muxed Address/Data

Unmuxed Address

Buffered Data

LA[27:31]

LAD[0:31]

LALE

LBCTL

Local Bus Interface

Latch

Buffer

Slower

memories

and

peripherals

SDRAM

SSRAM

DIR

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