MPC8540 datasheet(590/1302 Pages) FREESCALE

590 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-86

Freescale Semiconductor

Local Bus Controller

Figure 13-70. Local Bus Peripheral Hierarchy for Very High Bus Speeds

13.5.1.4

GPCM Timings

In case a system contains a memory hierarchy with high speed synchronous memories (SDRAM,

synchronous SRAM) and lower speed asynchronous memories (for example, FLASH EPROM

and peripherals) the GPCM-controlled memories should be decoupled by buffers to reduce

capacitive loading on the bus. Those buffers have to be taken into account for the timing

calculations.

Figure 13-71. GPCM Address Timings

To calculate address setup timing for a slower peripheral/memory device, several parameters have

to be added: propagation delay for the address latch, propagation delay for the buffer and the

address setup for the actual peripheral. Typical values for the two propagation delays are in the

order of 3–6 ns, so for a 166 MHz bus frequency, LCS should arrive on the order of 3 bus clocks

later.

Muxed Address/Data

Unmuxed Address

Buffered Data

LA[27:31]

LAD[0:31]

LALE

LBCTL

Local Bus Interface

Latch

Slower

memories

and

peripherals

SDRAM

A/D

DIR

Muxed Address/Data

Unmuxed Address

Buffered Address

Slower

memories

and

peripherals

Device

input

Buffer

Latch

LAD[0:31]

LALE

LBCTL

Local Bus Interface

MPC8540 Datasheet(PDF) 590 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 590 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL