MPC8540 datasheet(591/1302 Pages) FREESCALE

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Initialization/Application Information

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

13-87

For data timings, only the propagation delay of one buffer plus the actual data setup time has to be

considered.

Figure 13-72. GPCM Data timings

13.5.2 Bus Turnaround

Because the local bus uses multiplexed address and data, special consideration must be given to

avoid bus contention at bus turnaround. The following cases must be examined:

•

Address phase after previous read

•

Read data phase after address phase

•

Read-modify-write cycle for parity protected memory banks

•

UPM cycles with additional address phases

The bus does not change direction for the following cases so they need no special attention:

•

Continued burst after the first beat

•

Write data phase after address phase

•

Address phase after previous write

13.5.2.1

Address Phase After Previous Read

During a read cycle, the memory/peripheral drives the bus and the bus transceiver drives LAD.

After the data has been sampled, the output drivers of the external device must be disabled. This

can take some time; for slow devices the EHTR feature of the GPCM or the programmability of

the UPM should be used to guarantee that those devices have stopped driving the bus when the

LBC memory controller ends the bus cycle.

In this case, after the previous cycle ends, LBCTL goes high and changes the direction of the bus

transceiver. The LBC then inserts a bus turnaround cycle to avoid contention. The external device

has now already placed its data signals in high impedance and no bus contention will occur.

Muxed Address/Data

Buffered Data

LAD[0:31]

LBCTL

Local Bus Interface

Buffer

Slower

memories

and

peripherals

Device

input

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