MPC8540 datasheet(594/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

13-90

Freescale Semiconductor

Local Bus Controller

13.5.4 Interfacing to SDRAM

The following subsections provide application information on interfacing to SDRAM.

13.5.4.1

Basic SDRAM Capabilities of the Local Bus

The LBC provides one SDRAM machine for the local bus. Although there is only one machine,

multiple chip selects (LCSn) can be programmed to support multiple SDRAM devices. Note that

no limitation exists on the number of chip selects that can be programmed for SDRAM. This

means that LCS[1:7] can be programmed to support SDRAM, assuming LCS0 is reserved for the

GPCM to connect to Flash memory.

If multiple chip selects are configured to support SDRAM on the local bus, each SDRAM device

should have the same port size and timing parameters. This means that all option registers (ORn)

for the SDRAM chip selects should be programmed exactly the same.

NOTE

Although in principle it is possible to mix different port sizes and

timing parameters, combinations are limited and this operation is not

recommended.

Half Word

000

OP0

OP1

—

OP0

OP1

OP0

001

—

OP1

OP2

—

OP1

010

—

OP2

OP3

OP2

OP3

OP2

100

OP4

OP5

—

OP4

OP5

OP4

101

—

OP5

OP6

—

OP5

110

—

OP6

OP7

OP6

OP7

OP6

Word

000

OP0

OP1

OP2

OP3

OP0

OP1

OP0

100

OP4

OP5

OP6

OP7

OP4

OP5

OP4

1 Address state is the calculated address for port size.

2 OPn: These lanes are read or written during that bus transaction. OP0 is the

most-significant byte of a word operand and OP3 is the least-significant byte.

3 — Denotes a byte not driven during that write cycle.

Table 13-33. Data Bus Requirements For Read Cycle (continued)

Transfer

Size

Address

State 1

A[29:31]

Port Size/Data Bus Assignments

32-Bit

16-Bit

8-Bit

0–7

8–15

16–23

24–31

0–7

8–15

0–7

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